Home
last modified time | relevance | path

Searched refs:SDMMC_CLKCR_DDR_Pos (Results 1 – 25 of 81) sorted by relevance

1234

/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h17297 #define SDMMC_CLKCR_DDR_Pos (18U) macro
17298 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32l562xx.h18068 #define SDMMC_CLKCR_DDR_Pos (18U) macro
18069 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h10403 #define SDMMC_CLKCR_DDR_Pos (18U) macro
10404 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000…
Dstm32h562xx.h11129 #define SDMMC_CLKCR_DDR_Pos (18U) macro
11130 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000…
Dstm32h533xx.h10812 #define SDMMC_CLKCR_DDR_Pos (18U) macro
10813 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000…
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l4r5xx.h14213 #define SDMMC_CLKCR_DDR_Pos (18U) macro
14214 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32l4r7xx.h14712 #define SDMMC_CLKCR_DDR_Pos (18U) macro
14713 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32l4s5xx.h14560 #define SDMMC_CLKCR_DDR_Pos (18U) macro
14561 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32l4s7xx.h15059 #define SDMMC_CLKCR_DDR_Pos (18U) macro
15060 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32l4p5xx.h15197 #define SDMMC_CLKCR_DDR_Pos (18U) macro
15198 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32l4q5xx.h15708 #define SDMMC_CLKCR_DDR_Pos (18U) macro
15709 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h16284 #define SDMMC_CLKCR_DDR_Pos (18U) macro
16285 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32h7b0xx.h16764 #define SDMMC_CLKCR_DDR_Pos (18U) macro
16765 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32h7b0xxq.h16776 #define SDMMC_CLKCR_DDR_Pos (18U) macro
16777 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32h7a3xxq.h16296 #define SDMMC_CLKCR_DDR_Pos (18U) macro
16297 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32h7b3xx.h16771 #define SDMMC_CLKCR_DDR_Pos (18U) macro
16772 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32h7b3xxq.h16783 #define SDMMC_CLKCR_DDR_Pos (18U) macro
16784 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32h730xxq.h18350 #define SDMMC_CLKCR_DDR_Pos (18U) macro
18351 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32h733xx.h18338 #define SDMMC_CLKCR_DDR_Pos (18U) macro
18339 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
Dstm32h725xx.h17863 #define SDMMC_CLKCR_DDR_Pos (18U) macro
17864 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h11494 #define SDMMC_CLKCR_DDR_Pos (18U) macro
11495 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000…
Dstm32u535xx.h11094 #define SDMMC_CLKCR_DDR_Pos (18U) macro
11095 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000…
Dstm32u575xx.h12129 #define SDMMC_CLKCR_DDR_Pos (18U) macro
12130 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h17879 #define SDMMC_CLKCR_DDR_Pos (18U) macro
17880 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x…
Dstm32h7s7xx.h19194 #define SDMMC_CLKCR_DDR_Pos (18U) macro
19195 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x…

1234