Searched refs:RNG_CR_CLKDIV_15_0_Pos (Results 1 – 2 of 2) sorted by relevance
4154 #define RNG_CR_CLKDIV_15_0_Pos (8UL) /*!<RNG CR: CLK… macro4157 …RNG_CR_CLKDIV_15_0_0 (0x1U << RNG_CR_CLKDIV_15_0_Pos)4158 …RNG_CR_CLKDIV_15_0_1 (0x2U << RNG_CR_CLKDIV_15_0_Pos)4159 …RNG_CR_CLKDIV_15_0_2 (0x4U << RNG_CR_CLKDIV_15_0_Pos)4160 …RNG_CR_CLKDIV_15_0_3 (0x8U << RNG_CR_CLKDIV_15_0_Pos)4161 …NG_CR_CLKDIV_15_0_4 (0x10U << RNG_CR_CLKDIV_15_0_Pos)4162 …NG_CR_CLKDIV_15_0_5 (0x20U << RNG_CR_CLKDIV_15_0_Pos)4163 …NG_CR_CLKDIV_15_0_6 (0x40U << RNG_CR_CLKDIV_15_0_Pos)4164 …NG_CR_CLKDIV_15_0_7 (0x80U << RNG_CR_CLKDIV_15_0_Pos)4165 …G_CR_CLKDIV_15_0_8 (0x100U << RNG_CR_CLKDIV_15_0_Pos)[all …]
666 MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV_15_0, value << RNG_CR_CLKDIV_15_0_Pos); in LL_RNG_SetSamplingClockEnableDivider()677 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_CLKDIV_15_0) >> RNG_CR_CLKDIV_15_0_Pos); in LL_RNG_GetSamplingClockEnableDivider()
