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Searched refs:RISAF_REGx_zCFGR_SRCID_Pos (Results 1 – 5 of 5) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rif.c829 … | (cid << RISAF_REGx_zCFGR_SRCID_Pos) | (pConfig->SecPriv << RISAF_REGx_zCFGR_SEC_Pos) in HAL_RIF_RISAF_ConfigSubRegion()
854 … | (cid << RISAF_REGx_zCFGR_SRCID_Pos) | (pConfig->SecPriv << RISAF_REGx_zCFGR_SEC_Pos) in HAL_RIF_RISAF_ConfigSubRegion()
915 cid = ((cfgr_reg & RISAF_REGx_zCFGR_SRCID) >> RISAF_REGx_zCFGR_SRCID_Pos); in HAL_RIF_RISAF_GetConfigSubRegion()
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h32255 #define RISAF_REGx_zCFGR_SRCID_Pos (4U) macro
32256 #define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
32258 #define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
32259 #define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
32260 #define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
Dstm32n657xx.h33620 #define RISAF_REGx_zCFGR_SRCID_Pos (4U) macro
33621 #define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
33623 #define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
33624 #define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
33625 #define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
Dstm32n655xx.h33288 #define RISAF_REGx_zCFGR_SRCID_Pos (4U) macro
33289 #define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
33291 #define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
33292 #define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
33293 #define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
Dstm32n647xx.h32587 #define RISAF_REGx_zCFGR_SRCID_Pos (4U) macro
32588 #define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
32590 #define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
32591 #define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …
32592 #define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< …