Searched refs:RCC_USBPHYCLKSOURCE_PLL1_DIV2 (Results 1 – 2 of 2) sorted by relevance
312 ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1_DIV2))1239 case RCC_USBPHYCLKSOURCE_PLL1_DIV2: /* PLL1 P divider clock div 2 selected as USB PHY clock */ in HAL_RCCEx_PeriphCLKConfig()3051 else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1_DIV2) /* PLL1P_DIV2 */ in HAL_RCCEx_GetPeriphCLKFreq()
955 #define RCC_USBPHYCLKSOURCE_PLL1_DIV2 (RCC_CCIPR2_USBPHYCSEL_1 | RCC_CCIPR2_USBPHYCSEL_0) /*!< PLL… macro
