Searched refs:RCC_PLLSOURCE_HSI_DIV2 (Results 1 – 3 of 3) sorted by relevance
420 if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) in HAL_RCCEx_GetPeriphCLKFreq()451 if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) in HAL_RCCEx_GetPeriphCLKFreq()
420 …) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) in HAL_RCC_OscConfig()1113 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) in HAL_RCC_GetSysClockFreq()
93 #define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL ent… macro1315 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \