RCC_PLLCKSELR_DIVM3_Pos (reference) in projects: hal_stm32-latest

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Searched refs:RCC_PLLCKSELR_DIVM3_Pos (Results 1 – 25 of 32) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
D	stm32h7rsxx_hal_rcc.c	`1793 RCC_OscInitStruct->PLL3.PLLM = ((regvalue & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); in HAL_RCC_GetOscConfig() 2258 pllm = (tmpreg1 & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos; in RCC_PLL3_GetVCOOutputFreq()`
D	stm32h7rsxx_ll_rcc.c	`202 …<< RCC_PLLCKSELR_DIVM1_Pos) \| (32U << RCC_PLLCKSELR_DIVM2_Pos) \| (32U << RCC_PLLCKSELR_DIVM3_Pos)); in LL_RCC_DeInit()`
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
D	stm32h7rsxx_ll_rcc.h	`5002 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); in LL_RCC_PLL3_GetM() 5074 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos); in LL_RCC_PLL3_SetM()`
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
D	stm32h7xx_ll_rcc.h	`5147 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); in LL_RCC_PLL3_GetM() 5209 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos); in LL_RCC_PLL3_SetM()`
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
D	stm32h7xx_hal_rcc_ex.c	`1742 …lkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); in HAL_RCCEx_GetPeriphCLKConfig()`
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
D	stm32h7a3xx.h	13039 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 13040 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 13042 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 13043 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 13044 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 13045 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 13046 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 13047 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h7b0xx.h	13483 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 13484 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 13486 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 13487 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 13488 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 13489 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 13490 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 13491 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h7b0xxq.h	13495 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 13496 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 13498 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 13499 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 13500 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 13501 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 13502 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 13503 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h7a3xxq.h	13051 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 13052 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 13054 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 13055 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 13056 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 13057 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 13058 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 13059 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h7b3xx.h	13490 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 13491 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 13493 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 13494 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 13495 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 13496 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 13497 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 13498 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h7b3xxq.h	13502 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 13503 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 13505 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 13506 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 13507 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 13508 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 13509 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 13510 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h730xxq.h	15351 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 15352 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 15354 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 15355 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 15356 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 15357 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 15358 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 15359 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h733xx.h	15339 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 15340 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 15342 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 15343 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 15344 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 15345 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 15346 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 15347 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h725xx.h	14900 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 14901 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 14903 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 14904 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 14905 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 14906 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 14907 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 14908 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h730xx.h	15339 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 15340 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 15342 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 15343 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 15344 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 15345 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 15346 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 15347 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h735xx.h	15351 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 15352 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 15354 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 15355 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 15356 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 15357 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 15358 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 15359 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h742xx.h	14225 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 14226 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 14228 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 14229 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 14230 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 14231 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 14232 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 14233 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h723xx.h	14888 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 14889 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 14891 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 14892 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 14893 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 14894 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 14895 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 14896 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h750xx.h	15118 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 15119 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 15121 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 15122 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 15123 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 15124 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 15125 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 15126 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h753xx.h	15124 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 15125 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 15127 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 15128 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 15129 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 15130 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 15131 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 15132 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
D	stm32h745xx.h	15431 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 15432 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 … 15434 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 … 15435 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 … 15436 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 … 15437 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 … 15438 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 … 15439 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 …
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
D	stm32h7r3xx.h	14755 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 14756 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 / 14758 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 / 14759 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 / 14760 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 / 14761 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 / 14762 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 / 14763 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x02000000 /
D	stm32h7s7xx.h	15789 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 15790 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 / 15792 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 / 15793 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 / 15794 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 / 15795 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 / 15796 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 / 15797 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x02000000 /
D	stm32h7s3xx.h	15387 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 15388 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 / 15390 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 / 15391 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 / 15392 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 / 15393 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 / 15394 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 / 15395 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x02000000 /
D	stm32h7r7xx.h	15155 #define RCC_PLLCKSELR_DIVM3_Pos (20U) macro 15156 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x03F00000 / 15158 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00100000 / 15159 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00200000 / 15160 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00400000 / 15161 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x00800000 / 15162 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x01000000 / 15163 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /!< 0x02000000 /

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mcuboot-latest
mipi-sys-t-latest
net-tools-latest
nrf_hw_models-latest
nrf_wifi-latest
open-amp-latest
openthread-latest
percepio-latest
picolibc-latest
segger-latest
tinycrypt-latest
trusted-firmware-a-latest
trusted-firmware-m-latest
uoscore-uedhoc-latest
zcbor-latest