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Searched refs:RCC_PLLCFGR_PLL1SEN (Results 1 – 7 of 7) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_rcc.h3811 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN); in LL_RCC_PLL1S_Enable()
3861 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN) == RCC_PLLCFGR_PLL1SEN) ? 1UL : 0UL); in LL_RCC_PLL1S_IsEnabled()
3915 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN); in LL_RCC_PLL1S_Disable()
Dstm32h7rsxx_hal_rcc.h296 #define RCC_PLL_SCLK RCC_PLLCFGR_PLL1SEN /*!< PLL DIVS divider output enable */
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_rcc.c1951 …->PLLCFGR, (RCC_PLLCFGR_PLL1PEN | RCC_PLLCFGR_PLL1QEN | RCC_PLLCFGR_PLL1REN | RCC_PLLCFGR_PLL1SEN | in RCC_PLL_Config()
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h14792 #define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divid… macro
Dstm32h7s7xx.h15826 #define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divid… macro
Dstm32h7s3xx.h15424 #define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divid… macro
Dstm32h7r7xx.h15192 #define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divid… macro