Searched refs:RCC_PLLCFGR_PLL1SEN (Results 1 – 7 of 7) sorted by relevance
3811 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN); in LL_RCC_PLL1S_Enable()3861 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN) == RCC_PLLCFGR_PLL1SEN) ? 1UL : 0UL); in LL_RCC_PLL1S_IsEnabled()3915 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN); in LL_RCC_PLL1S_Disable()
296 #define RCC_PLL_SCLK RCC_PLLCFGR_PLL1SEN /*!< PLL DIVS divider output enable */
1951 …->PLLCFGR, (RCC_PLLCFGR_PLL1PEN | RCC_PLLCFGR_PLL1QEN | RCC_PLLCFGR_PLL1REN | RCC_PLLCFGR_PLL1SEN | in RCC_PLL_Config()
14792 #define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divid… macro
15826 #define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divid… macro
15424 #define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divid… macro
15192 #define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divid… macro