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Searched refs:RCC_PLLCFGR_PLL1RGE_Pos (Results 1 – 25 of 29) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_rcc.c2022 pllvco = (pllvco << ((RCC_PLLCFGR_PLL2RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos) * PLLnumber)); in RCC_PLL_Config()
2035 …VCOSEL | RCC_PLLCFGR_PLL1FRACEN) << (((RCC_PLLCFGR_PLL2RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos)*PLLnumbe… in RCC_PLL_Config()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_rcc.h4123 …PLLCFGR_PLL2RGE, ((__PLL_VCOINPUT_RANGE__) << (RCC_PLLCFGR_PLL2RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos)))
4261 …PLLCFGR_PLL3RGE, ((__PLL_VCOINPUT_RANGE__) << (RCC_PLLCFGR_PLL3RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos)))
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h13057 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
13058 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
13060 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
13061 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
13062 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
13063 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h7b0xx.h13501 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
13502 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
13504 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
13505 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
13506 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
13507 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h7b0xxq.h13513 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
13514 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
13516 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
13517 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
13518 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
13519 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h7a3xxq.h13069 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
13070 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
13072 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
13073 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
13074 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
13075 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h7b3xx.h13508 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
13509 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
13511 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
13512 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
13513 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
13514 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h7b3xxq.h13520 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
13521 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
13523 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
13524 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
13525 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
13526 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h730xxq.h15369 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
15370 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
15372 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
15373 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
15374 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
15375 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h733xx.h15357 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
15358 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
15360 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
15361 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
15362 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
15363 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h725xx.h14918 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
14919 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
14921 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
14922 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
14923 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
14924 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h730xx.h15357 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
15358 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
15360 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
15361 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
15362 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
15363 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h735xx.h15369 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
15370 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
15372 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
15373 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
15374 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
15375 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h742xx.h14243 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
14244 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
14246 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
14247 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
14248 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
14249 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h723xx.h14906 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
14907 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
14909 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
14910 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
14911 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
14912 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h750xx.h15136 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
15137 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
15139 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
15140 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
15141 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
15142 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h753xx.h15142 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
15143 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
15145 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
15146 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
15147 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
15148 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h745xx.h15449 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
15450 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
15452 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
15453 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
15454 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
15455 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h745xg.h15449 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
15450 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
15452 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
15453 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
15454 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
15455 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h743xx.h14873 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
14874 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
14876 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
14877 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
14878 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
14879 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h755xx.h15718 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
15719 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
15721 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
15722 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
15723 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
15724 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h757xx.h18875 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
18876 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
18878 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
18879 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
18880 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
18881 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h747xg.h18606 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
18607 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
18609 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
18610 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
18611 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
18612 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
Dstm32h747xx.h18606 #define RCC_PLLCFGR_PLL1RGE_Pos (2U) macro
18607 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
18609 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
18610 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
18611 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
18612 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h4501 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos); in LL_RCC_PLL1_SetVCOInputRange()

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