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Searched refs:RCC_PLLCFGR_PLL1RGE_1 (Results 1 – 25 of 29) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_rcc.h1102 #define LL_RCC_PLLINPUTRANGE_4_8 RCC_PLLCFGR_PLL1RGE_1
1103 #define LL_RCC_PLLINPUTRANGE_8_16 (RCC_PLLCFGR_PLL1RGE_1 | RCC_PLLCFGR_PLL1RGE_0)
Dstm32h7rsxx_hal_rcc.h307 #define RCC_PLL_VCOINPUT_RANGE2 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency for PL…
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc.h288 #define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency be…
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h13061 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h7b0xx.h13505 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h7b0xxq.h13517 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h7a3xxq.h13073 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h7b3xx.h13512 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h7b3xxq.h13524 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h730xxq.h15373 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h733xx.h15361 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h725xx.h14922 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h730xx.h15361 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h735xx.h15373 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h742xx.h14247 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h723xx.h14910 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h750xx.h15140 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h753xx.h15146 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h745xx.h15453 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h745xg.h15453 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
Dstm32h743xx.h14877 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */ macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h14779 #define RCC_PLLCFGR_PLL1RGE_1 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000010 */ macro
Dstm32h7s7xx.h15813 #define RCC_PLLCFGR_PLL1RGE_1 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000010 */ macro
Dstm32h7s3xx.h15411 #define RCC_PLLCFGR_PLL1RGE_1 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000010 */ macro
Dstm32h7r7xx.h15179 #define RCC_PLLCFGR_PLL1RGE_1 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000010 */ macro

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