Searched refs:RCC_PLLCFGR_PLL1REN (Results 1 – 7 of 7) sorted by relevance
3800 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1REN); in LL_RCC_PLL1R_Enable()3851 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1REN) == RCC_PLLCFGR_PLL1REN) ? 1UL : 0UL); in LL_RCC_PLL1R_IsEnabled()3904 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1REN); in LL_RCC_PLL1R_Disable()
295 #define RCC_PLL_RCLK RCC_PLLCFGR_PLL1REN /*!< PLL DIVR divider output enable */
1951 …CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLL1PEN | RCC_PLLCFGR_PLL1QEN | RCC_PLLCFGR_PLL1REN | RCC_PLL… in RCC_PLL_Config()
14789 #define RCC_PLLCFGR_PLL1REN RCC_PLLCFGR_PLL1REN_Msk /*!< PLL1 DIVR divid… macro
15823 #define RCC_PLLCFGR_PLL1REN RCC_PLLCFGR_PLL1REN_Msk /*!< PLL1 DIVR divid… macro
15421 #define RCC_PLLCFGR_PLL1REN RCC_PLLCFGR_PLL1REN_Msk /*!< PLL1 DIVR divid… macro
15189 #define RCC_PLLCFGR_PLL1REN RCC_PLLCFGR_PLL1REN_Msk /*!< PLL1 DIVR divid… macro
