Searched refs:RCC_PLLCFGR_PLL1QEN (Results 1 – 7 of 7) sorted by relevance
3789 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1QEN); in LL_RCC_PLL1Q_Enable()3841 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1QEN) == RCC_PLLCFGR_PLL1QEN) ? 1UL : 0UL); in LL_RCC_PLL1Q_IsEnabled()3893 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1QEN); in LL_RCC_PLL1Q_Disable()
294 #define RCC_PLL_QCLK RCC_PLLCFGR_PLL1QEN /*!< PLL DIVQ divider output enable */
1951 …CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLL1PEN | RCC_PLLCFGR_PLL1QEN | RCC_PLLCFGR_PLL1REN | RCC_PLL… in RCC_PLL_Config()
14786 #define RCC_PLLCFGR_PLL1QEN RCC_PLLCFGR_PLL1QEN_Msk /*!< PLL1 DIVQ divid… macro
15820 #define RCC_PLLCFGR_PLL1QEN RCC_PLLCFGR_PLL1QEN_Msk /*!< PLL1 DIVQ divid… macro
15418 #define RCC_PLLCFGR_PLL1QEN RCC_PLLCFGR_PLL1QEN_Msk /*!< PLL1 DIVQ divid… macro
15186 #define RCC_PLLCFGR_PLL1QEN RCC_PLLCFGR_PLL1QEN_Msk /*!< PLL1 DIVQ divid… macro
