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Searched refs:RCC_PLL4CFGR3_PLL4PDIV2 (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c360 pllp2 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos; in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c417 pllp2 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos; in SystemCoreClockUpdate()
Dstm32n645xx.h25556 #define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO … macro
Dstm32n657xx.h26705 #define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO … macro
Dstm32n655xx.h26463 #define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO … macro
Dstm32n647xx.h25798 #define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO … macro
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_rcc.h3949 MODIFY_REG(RCC->PLL4CFGR3, (RCC_PLL4CFGR3_PLL4PDIV1 | RCC_PLL4CFGR3_PLL4PDIV2), \
3951 ((((__PLLP2__) << RCC_PLL4CFGR3_PLL4PDIV2_Pos) & RCC_PLL4CFGR3_PLL4PDIV2)))); \
Dstm32n6xx_ll_rcc.h6288 MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV2, P2 << RCC_PLL4CFGR3_PLL4PDIV2_Pos); in LL_RCC_PLL4_SetP2()
6298 …return (uint32_t)(READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos… in LL_RCC_PLL4_GetP2()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c1755 …pRCC_OscInitStruct->PLL4.PLLP2 = ((cfgr_value & RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV… in HAL_RCC_GetOscConfig()