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Searched refs:RCC_PLL4CFGR3_PLL4PDIV1_Pos (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c359 pllp1 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos; in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c416 pllp1 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos; in SystemCoreClockUpdate()
Dstm32n645xx.h25557 #define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27U) macro
25558 #define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x380000…
Dstm32n657xx.h26706 #define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27U) macro
26707 #define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x380000…
Dstm32n655xx.h26464 #define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27U) macro
26465 #define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x380000…
Dstm32n647xx.h25799 #define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27U) macro
25800 #define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x380000…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c1754 …scInitStruct->PLL4.PLLP1 = ((cfgr_value & RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h6267 MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV1, P1 << RCC_PLL4CFGR3_PLL4PDIV1_Pos); in LL_RCC_PLL4_SetP1()
6277 …eturn (uint32_t)(READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos); in LL_RCC_PLL4_GetP1()
Dstm32n6xx_hal_rcc.h3950 ((((__PLLP1__) << RCC_PLL4CFGR3_PLL4PDIV1_Pos) & RCC_PLL4CFGR3_PLL4PDIV1) | \