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Searched refs:RCC_PLL4CFGR1_PLL4DIVN_Pos (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c356 plln = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos; in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c413 plln = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos; in SystemCoreClockUpdate()
Dstm32n645xx.h25511 #define RCC_PLL4CFGR1_PLL4DIVN_Pos (8U) macro
25512 #define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000F…
Dstm32n657xx.h26660 #define RCC_PLL4CFGR1_PLL4DIVN_Pos (8U) macro
26661 #define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000F…
Dstm32n655xx.h26418 #define RCC_PLL4CFGR1_PLL4DIVN_Pos (8U) macro
26419 #define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000F…
Dstm32n647xx.h25753 #define RCC_PLL4CFGR1_PLL4DIVN_Pos (8U) macro
25754 #define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000F…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c1750 …C_OscInitStruct->PLL4.PLLN = ((cfgr_value & RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h6224 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVN, N << RCC_PLL4CFGR1_PLL4DIVN_Pos); in LL_RCC_PLL4_SetN()
6235 …return (uint32_t)((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos)… in LL_RCC_PLL4_GetN()
Dstm32n6xx_hal_rcc.h3947 … | ( (__PLLM__) << RCC_PLL4CFGR1_PLL4DIVM_Pos) | (((__PLLN__) << RCC_PLL4CFGR1_PLL4DIVN_Pos)))); \