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Searched refs:RCC_PLL4CFGR1_PLL4DIVM_Pos (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c355 pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos; in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c412 pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos; in SystemCoreClockUpdate()
Dstm32n645xx.h25514 #define RCC_PLL4CFGR1_PLL4DIVM_Pos (20U) macro
25515 #define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F000…
Dstm32n657xx.h26663 #define RCC_PLL4CFGR1_PLL4DIVM_Pos (20U) macro
26664 #define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F000…
Dstm32n655xx.h26421 #define RCC_PLL4CFGR1_PLL4DIVM_Pos (20U) macro
26422 #define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F000…
Dstm32n647xx.h25756 #define RCC_PLL4CFGR1_PLL4DIVM_Pos (20U) macro
25757 #define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F000…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c1749 …C_OscInitStruct->PLL4.PLLM = ((cfgr_value & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h6246 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM, M << RCC_PLL4CFGR1_PLL4DIVM_Pos); in LL_RCC_PLL4_SetM()
6256 return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos); in LL_RCC_PLL4_GetM()
Dstm32n6xx_hal_rcc.h3947 …((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL4CFGR1_PLL4DIVM_Pos) | (((__PLLN__) << RCC_PLL4CFGR1_PLL…