Searched refs:RCC_PLL4CFGR1_PLL4DIVM (Results 1 – 9 of 9) sorted by relevance
355 pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos; in SystemCoreClockUpdate()
412 pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos; in SystemCoreClockUpdate()
25516 #define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 refe… macro
26665 #define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 refe… macro
26423 #define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 refe… macro
25758 #define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 refe… macro
1749 …pRCC_OscInitStruct->PLL4.PLLM = ((cfgr_value & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_P… in HAL_RCC_GetOscConfig()
6246 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM, M << RCC_PLL4CFGR1_PLL4DIVM_Pos); in LL_RCC_PLL4_SetM()6256 return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos); in LL_RCC_PLL4_GetM()
3946 …RCC->PLL4CFGR1, (RCC_PLL4CFGR1_PLL4SEL | RCC_PLL4CFGR1_PLL4BYP | RCC_PLL4CFGR1_PLL4DIVM | RCC_PLL4…