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Searched refs:RCC_PLL3DIVR_R3_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h5177 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1UL); in LL_RCC_PLL3_GetR()
5242 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R - 1UL) << RCC_PLL3DIVR_R3_Pos); in LL_RCC_PLL3_SetR()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_rcc_ex.h1756 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, ((__PLL3R__) - 1U) << RCC_PLL3DIVR_R3_Pos)
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc_ex.c1744 …PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) +… in HAL_RCCEx_GetPeriphCLKConfig()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h13172 #define RCC_PLL3DIVR_R3_Pos (24U) macro
13173 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h7b0xx.h13616 #define RCC_PLL3DIVR_R3_Pos (24U) macro
13617 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h7b0xxq.h13628 #define RCC_PLL3DIVR_R3_Pos (24U) macro
13629 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h7a3xxq.h13184 #define RCC_PLL3DIVR_R3_Pos (24U) macro
13185 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h7b3xx.h13623 #define RCC_PLL3DIVR_R3_Pos (24U) macro
13624 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h7b3xxq.h13635 #define RCC_PLL3DIVR_R3_Pos (24U) macro
13636 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h730xxq.h15484 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15485 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h733xx.h15472 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15473 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h725xx.h15033 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15034 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h730xx.h15472 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15473 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h735xx.h15484 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15485 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h742xx.h14358 #define RCC_PLL3DIVR_R3_Pos (24U) macro
14359 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h723xx.h15021 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15022 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h750xx.h15251 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15252 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h753xx.h15257 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15258 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h745xx.h15564 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15565 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h745xg.h15564 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15565 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h743xx.h14988 #define RCC_PLL3DIVR_R3_Pos (24U) macro
14989 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h755xx.h15833 #define RCC_PLL3DIVR_R3_Pos (24U) macro
15834 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h757xx.h18990 #define RCC_PLL3DIVR_R3_Pos (24U) macro
18991 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h747xg.h18721 #define RCC_PLL3DIVR_R3_Pos (24U) macro
18722 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
Dstm32h747xx.h18721 #define RCC_PLL3DIVR_R3_Pos (24U) macro
18722 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */