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Searched refs:RCC_PLL3DIVR_Q3_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h5167 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1UL); in LL_RCC_PLL3_GetQ()
5231 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q - 1UL) << RCC_PLL3DIVR_Q3_Pos); in LL_RCC_PLL3_SetQ()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_rcc_ex.h1741 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, ((__PLL3Q__) - 1U) << RCC_PLL3DIVR_Q3_Pos)
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc_ex.c1746 …PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) +… in HAL_RCCEx_GetPeriphCLKConfig()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h13169 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
13170 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h7b0xx.h13613 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
13614 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h7b0xxq.h13625 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
13626 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h7a3xxq.h13181 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
13182 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h7b3xx.h13620 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
13621 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h7b3xxq.h13632 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
13633 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h730xxq.h15481 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15482 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h733xx.h15469 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15470 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h725xx.h15030 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15031 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h730xx.h15469 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15470 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h735xx.h15481 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15482 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h742xx.h14355 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
14356 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h723xx.h15018 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15019 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h750xx.h15248 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15249 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h753xx.h15254 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15255 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h745xx.h15561 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15562 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h745xg.h15561 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15562 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h743xx.h14985 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
14986 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h755xx.h15830 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
15831 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h757xx.h18987 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
18988 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h747xg.h18718 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
18719 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
Dstm32h747xx.h18718 #define RCC_PLL3DIVR_Q3_Pos (16U) macro
18719 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */