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Searched refs:RCC_PLL3DIVR_N3_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h5137 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1UL); in LL_RCC_PLL3_GetN()
5198 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N - 1UL) << RCC_PLL3DIVR_N3_Pos); in LL_RCC_PLL3_SetN()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_rcc_ex.h1696 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, ((__PLL3N__) - 1U) << RCC_PLL3DIVR_N3_Pos)
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc_ex.c1743 …PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) +… in HAL_RCCEx_GetPeriphCLKConfig()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h13163 #define RCC_PLL3DIVR_N3_Pos (0U) macro
13164 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h7b0xx.h13607 #define RCC_PLL3DIVR_N3_Pos (0U) macro
13608 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h7b0xxq.h13619 #define RCC_PLL3DIVR_N3_Pos (0U) macro
13620 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h7a3xxq.h13175 #define RCC_PLL3DIVR_N3_Pos (0U) macro
13176 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h7b3xx.h13614 #define RCC_PLL3DIVR_N3_Pos (0U) macro
13615 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h7b3xxq.h13626 #define RCC_PLL3DIVR_N3_Pos (0U) macro
13627 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h730xxq.h15475 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15476 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h733xx.h15463 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15464 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h725xx.h15024 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15025 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h730xx.h15463 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15464 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h735xx.h15475 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15476 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h742xx.h14349 #define RCC_PLL3DIVR_N3_Pos (0U) macro
14350 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h723xx.h15012 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15013 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h750xx.h15242 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15243 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h753xx.h15248 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15249 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h745xx.h15555 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15556 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h745xg.h15555 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15556 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h743xx.h14979 #define RCC_PLL3DIVR_N3_Pos (0U) macro
14980 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h755xx.h15824 #define RCC_PLL3DIVR_N3_Pos (0U) macro
15825 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h757xx.h18981 #define RCC_PLL3DIVR_N3_Pos (0U) macro
18982 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h747xg.h18712 #define RCC_PLL3DIVR_N3_Pos (0U) macro
18713 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
Dstm32h747xx.h18712 #define RCC_PLL3DIVR_N3_Pos (0U) macro
18713 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */