Searched refs:RCC_PLL3DIVR1_DIVR_Pos (Results 1 – 7 of 7) sorted by relevance
1626 pllr = ((RCC->PLL3DIVR1 & RCC_PLL3DIVR1_DIVR) >> RCC_PLL3DIVR1_DIVR_Pos) + 1U; in HAL_RCC_GetPLL3RFreq()1811 RCC_OscInitStruct->PLL3.PLLR = (((regvalue & RCC_PLL3DIVR1_DIVR) >> RCC_PLL3DIVR1_DIVR_Pos) + 1U); in HAL_RCC_GetOscConfig()
5032 …return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVR) >> RCC_PLL3DIVR1_DIVR_Pos) + 1UL); in LL_RCC_PLL3_GetR()5107 MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVR, (R - 1UL) << RCC_PLL3DIVR1_DIVR_Pos); in LL_RCC_PLL3_SetR()
4228 … ((((__PLL3R__) - 1U) << RCC_PLL3DIVR1_DIVR_Pos) & RCC_PLL3DIVR1_DIVR))); \
14993 #define RCC_PLL3DIVR1_DIVR_Pos (24U) macro14994 #define RCC_PLL3DIVR1_DIVR_Msk (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x7F000000 */14996 #define RCC_PLL3DIVR1_DIVR_0 (0x001UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x01000000 */14997 #define RCC_PLL3DIVR1_DIVR_1 (0x002UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x02000000 */14998 #define RCC_PLL3DIVR1_DIVR_2 (0x004UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x04000000 */14999 #define RCC_PLL3DIVR1_DIVR_3 (0x008UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x08000000 */15000 #define RCC_PLL3DIVR1_DIVR_4 (0x010UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x10000000 */15001 #define RCC_PLL3DIVR1_DIVR_5 (0x020UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x20000000 */15002 #define RCC_PLL3DIVR1_DIVR_6 (0x040UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x40000000 */
16027 #define RCC_PLL3DIVR1_DIVR_Pos (24U) macro16028 #define RCC_PLL3DIVR1_DIVR_Msk (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x7F000000 */16030 #define RCC_PLL3DIVR1_DIVR_0 (0x001UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x01000000 */16031 #define RCC_PLL3DIVR1_DIVR_1 (0x002UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x02000000 */16032 #define RCC_PLL3DIVR1_DIVR_2 (0x004UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x04000000 */16033 #define RCC_PLL3DIVR1_DIVR_3 (0x008UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x08000000 */16034 #define RCC_PLL3DIVR1_DIVR_4 (0x010UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x10000000 */16035 #define RCC_PLL3DIVR1_DIVR_5 (0x020UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x20000000 */16036 #define RCC_PLL3DIVR1_DIVR_6 (0x040UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x40000000 */
15625 #define RCC_PLL3DIVR1_DIVR_Pos (24U) macro15626 #define RCC_PLL3DIVR1_DIVR_Msk (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x7F000000 */15628 #define RCC_PLL3DIVR1_DIVR_0 (0x001UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x01000000 */15629 #define RCC_PLL3DIVR1_DIVR_1 (0x002UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x02000000 */15630 #define RCC_PLL3DIVR1_DIVR_2 (0x004UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x04000000 */15631 #define RCC_PLL3DIVR1_DIVR_3 (0x008UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x08000000 */15632 #define RCC_PLL3DIVR1_DIVR_4 (0x010UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x10000000 */15633 #define RCC_PLL3DIVR1_DIVR_5 (0x020UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x20000000 */15634 #define RCC_PLL3DIVR1_DIVR_6 (0x040UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x40000000 */
15393 #define RCC_PLL3DIVR1_DIVR_Pos (24U) macro15394 #define RCC_PLL3DIVR1_DIVR_Msk (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x7F000000 */15396 #define RCC_PLL3DIVR1_DIVR_0 (0x001UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x01000000 */15397 #define RCC_PLL3DIVR1_DIVR_1 (0x002UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x02000000 */15398 #define RCC_PLL3DIVR1_DIVR_2 (0x004UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x04000000 */15399 #define RCC_PLL3DIVR1_DIVR_3 (0x008UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x08000000 */15400 #define RCC_PLL3DIVR1_DIVR_4 (0x010UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x10000000 */15401 #define RCC_PLL3DIVR1_DIVR_5 (0x020UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x20000000 */15402 #define RCC_PLL3DIVR1_DIVR_6 (0x040UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x40000000 */
