Searched refs:RCC_PLL3DIVR1_DIVQ_Pos (Results 1 – 7 of 7) sorted by relevance
1611 pllq = ((RCC->PLL3DIVR1 & RCC_PLL3DIVR1_DIVQ) >> RCC_PLL3DIVR1_DIVQ_Pos) + 1U; in HAL_RCC_GetPLL3QFreq()1813 RCC_OscInitStruct->PLL3.PLLQ = (((regvalue & RCC_PLL3DIVR1_DIVQ) >> RCC_PLL3DIVR1_DIVQ_Pos) + 1U); in HAL_RCC_GetOscConfig()
5022 …return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVQ) >> RCC_PLL3DIVR1_DIVQ_Pos) + 1UL); in LL_RCC_PLL3_GetQ()5096 MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVQ, (Q - 1UL) << RCC_PLL3DIVR1_DIVQ_Pos); in LL_RCC_PLL3_SetQ()
4227 … ((((__PLL3Q__) - 1U) << RCC_PLL3DIVR1_DIVQ_Pos) & RCC_PLL3DIVR1_DIVQ) | \
14982 #define RCC_PLL3DIVR1_DIVQ_Pos (16U) macro14983 #define RCC_PLL3DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x007F0000 */14985 #define RCC_PLL3DIVR1_DIVQ_0 (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00010000 */14986 #define RCC_PLL3DIVR1_DIVQ_1 (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00020000 */14987 #define RCC_PLL3DIVR1_DIVQ_2 (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00040000 */14988 #define RCC_PLL3DIVR1_DIVQ_3 (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00080000 */14989 #define RCC_PLL3DIVR1_DIVQ_4 (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00100000 */14990 #define RCC_PLL3DIVR1_DIVQ_5 (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00200000 */14991 #define RCC_PLL3DIVR1_DIVQ_6 (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00400000 */
16016 #define RCC_PLL3DIVR1_DIVQ_Pos (16U) macro16017 #define RCC_PLL3DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x007F0000 */16019 #define RCC_PLL3DIVR1_DIVQ_0 (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00010000 */16020 #define RCC_PLL3DIVR1_DIVQ_1 (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00020000 */16021 #define RCC_PLL3DIVR1_DIVQ_2 (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00040000 */16022 #define RCC_PLL3DIVR1_DIVQ_3 (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00080000 */16023 #define RCC_PLL3DIVR1_DIVQ_4 (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00100000 */16024 #define RCC_PLL3DIVR1_DIVQ_5 (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00200000 */16025 #define RCC_PLL3DIVR1_DIVQ_6 (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00400000 */
15614 #define RCC_PLL3DIVR1_DIVQ_Pos (16U) macro15615 #define RCC_PLL3DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x007F0000 */15617 #define RCC_PLL3DIVR1_DIVQ_0 (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00010000 */15618 #define RCC_PLL3DIVR1_DIVQ_1 (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00020000 */15619 #define RCC_PLL3DIVR1_DIVQ_2 (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00040000 */15620 #define RCC_PLL3DIVR1_DIVQ_3 (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00080000 */15621 #define RCC_PLL3DIVR1_DIVQ_4 (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00100000 */15622 #define RCC_PLL3DIVR1_DIVQ_5 (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00200000 */15623 #define RCC_PLL3DIVR1_DIVQ_6 (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00400000 */
15382 #define RCC_PLL3DIVR1_DIVQ_Pos (16U) macro15383 #define RCC_PLL3DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x007F0000 */15385 #define RCC_PLL3DIVR1_DIVQ_0 (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00010000 */15386 #define RCC_PLL3DIVR1_DIVQ_1 (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00020000 */15387 #define RCC_PLL3DIVR1_DIVQ_2 (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00040000 */15388 #define RCC_PLL3DIVR1_DIVQ_3 (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00080000 */15389 #define RCC_PLL3DIVR1_DIVQ_4 (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00100000 */15390 #define RCC_PLL3DIVR1_DIVQ_5 (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00200000 */15391 #define RCC_PLL3DIVR1_DIVQ_6 (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00400000 */
