Searched refs:RCC_PLL3DIVR1_DIVP_Pos (Results 1 – 7 of 7) sorted by relevance
1596 pllp = ((RCC->PLL3DIVR1 & RCC_PLL3DIVR1_DIVP) >> RCC_PLL3DIVR1_DIVP_Pos) + 1U; in HAL_RCC_GetPLL3PFreq()1812 RCC_OscInitStruct->PLL3.PLLP = (((regvalue & RCC_PLL3DIVR1_DIVP) >> RCC_PLL3DIVR1_DIVP_Pos) + 1U); in HAL_RCC_GetOscConfig()
5012 …return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVP) >> RCC_PLL3DIVR1_DIVP_Pos) + 1UL); in LL_RCC_PLL3_GetP()5085 MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVP, (P - 1UL) << RCC_PLL3DIVR1_DIVP_Pos); in LL_RCC_PLL3_SetP()
4226 … ((((__PLL3P__) - 1U) << RCC_PLL3DIVR1_DIVP_Pos) & RCC_PLL3DIVR1_DIVP) | \
14971 #define RCC_PLL3DIVR1_DIVP_Pos (9U) macro14972 #define RCC_PLL3DIVR1_DIVP_Msk (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x0000FE00 */14974 #define RCC_PLL3DIVR1_DIVP_0 (0x001UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000200 */14975 #define RCC_PLL3DIVR1_DIVP_1 (0x002UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000400 */14976 #define RCC_PLL3DIVR1_DIVP_2 (0x004UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000800 */14977 #define RCC_PLL3DIVR1_DIVP_3 (0x008UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00001000 */14978 #define RCC_PLL3DIVR1_DIVP_4 (0x010UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00002000 */14979 #define RCC_PLL3DIVR1_DIVP_5 (0x020UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00004000 */14980 #define RCC_PLL3DIVR1_DIVP_6 (0x040UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00008000 */
16005 #define RCC_PLL3DIVR1_DIVP_Pos (9U) macro16006 #define RCC_PLL3DIVR1_DIVP_Msk (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x0000FE00 */16008 #define RCC_PLL3DIVR1_DIVP_0 (0x001UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000200 */16009 #define RCC_PLL3DIVR1_DIVP_1 (0x002UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000400 */16010 #define RCC_PLL3DIVR1_DIVP_2 (0x004UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000800 */16011 #define RCC_PLL3DIVR1_DIVP_3 (0x008UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00001000 */16012 #define RCC_PLL3DIVR1_DIVP_4 (0x010UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00002000 */16013 #define RCC_PLL3DIVR1_DIVP_5 (0x020UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00004000 */16014 #define RCC_PLL3DIVR1_DIVP_6 (0x040UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00008000 */
15603 #define RCC_PLL3DIVR1_DIVP_Pos (9U) macro15604 #define RCC_PLL3DIVR1_DIVP_Msk (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x0000FE00 */15606 #define RCC_PLL3DIVR1_DIVP_0 (0x001UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000200 */15607 #define RCC_PLL3DIVR1_DIVP_1 (0x002UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000400 */15608 #define RCC_PLL3DIVR1_DIVP_2 (0x004UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000800 */15609 #define RCC_PLL3DIVR1_DIVP_3 (0x008UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00001000 */15610 #define RCC_PLL3DIVR1_DIVP_4 (0x010UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00002000 */15611 #define RCC_PLL3DIVR1_DIVP_5 (0x020UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00004000 */15612 #define RCC_PLL3DIVR1_DIVP_6 (0x040UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00008000 */
15371 #define RCC_PLL3DIVR1_DIVP_Pos (9U) macro15372 #define RCC_PLL3DIVR1_DIVP_Msk (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x0000FE00 */15374 #define RCC_PLL3DIVR1_DIVP_0 (0x001UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000200 */15375 #define RCC_PLL3DIVR1_DIVP_1 (0x002UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000400 */15376 #define RCC_PLL3DIVR1_DIVP_2 (0x004UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000800 */15377 #define RCC_PLL3DIVR1_DIVP_3 (0x008UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00001000 */15378 #define RCC_PLL3DIVR1_DIVP_4 (0x010UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00002000 */15379 #define RCC_PLL3DIVR1_DIVP_5 (0x020UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00004000 */15380 #define RCC_PLL3DIVR1_DIVP_6 (0x040UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00008000 */
