Searched refs:RCC_PLL3DIVR1_DIVN_Pos (Results 1 – 5 of 5) sorted by relevance
4992 …return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVN) >> RCC_PLL3DIVR1_DIVN_Pos) + 1UL); in LL_RCC_PLL3_GetN()5063 MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVN, (N - 1UL) << RCC_PLL3DIVR1_DIVN_Pos); in LL_RCC_PLL3_SetN()
14958 #define RCC_PLL3DIVR1_DIVN_Pos (0U) macro14959 #define RCC_PLL3DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x000001FF */14961 #define RCC_PLL3DIVR1_DIVN_0 (0x001UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000001 */14962 #define RCC_PLL3DIVR1_DIVN_1 (0x002UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000002 */14963 #define RCC_PLL3DIVR1_DIVN_2 (0x004UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000004 */14964 #define RCC_PLL3DIVR1_DIVN_3 (0x008UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000008 */14965 #define RCC_PLL3DIVR1_DIVN_4 (0x010UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000010 */14966 #define RCC_PLL3DIVR1_DIVN_5 (0x020UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000020 */14967 #define RCC_PLL3DIVR1_DIVN_6 (0x040UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000040 */14968 #define RCC_PLL3DIVR1_DIVN_7 (0x080UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000080 */[all …]
15992 #define RCC_PLL3DIVR1_DIVN_Pos (0U) macro15993 #define RCC_PLL3DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x000001FF */15995 #define RCC_PLL3DIVR1_DIVN_0 (0x001UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000001 */15996 #define RCC_PLL3DIVR1_DIVN_1 (0x002UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000002 */15997 #define RCC_PLL3DIVR1_DIVN_2 (0x004UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000004 */15998 #define RCC_PLL3DIVR1_DIVN_3 (0x008UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000008 */15999 #define RCC_PLL3DIVR1_DIVN_4 (0x010UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000010 */16000 #define RCC_PLL3DIVR1_DIVN_5 (0x020UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000020 */16001 #define RCC_PLL3DIVR1_DIVN_6 (0x040UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000040 */16002 #define RCC_PLL3DIVR1_DIVN_7 (0x080UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000080 */[all …]
15590 #define RCC_PLL3DIVR1_DIVN_Pos (0U) macro15591 #define RCC_PLL3DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x000001FF */15593 #define RCC_PLL3DIVR1_DIVN_0 (0x001UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000001 */15594 #define RCC_PLL3DIVR1_DIVN_1 (0x002UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000002 */15595 #define RCC_PLL3DIVR1_DIVN_2 (0x004UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000004 */15596 #define RCC_PLL3DIVR1_DIVN_3 (0x008UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000008 */15597 #define RCC_PLL3DIVR1_DIVN_4 (0x010UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000010 */15598 #define RCC_PLL3DIVR1_DIVN_5 (0x020UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000020 */15599 #define RCC_PLL3DIVR1_DIVN_6 (0x040UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000040 */15600 #define RCC_PLL3DIVR1_DIVN_7 (0x080UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000080 */[all …]
15358 #define RCC_PLL3DIVR1_DIVN_Pos (0U) macro15359 #define RCC_PLL3DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x000001FF */15361 #define RCC_PLL3DIVR1_DIVN_0 (0x001UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000001 */15362 #define RCC_PLL3DIVR1_DIVN_1 (0x002UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000002 */15363 #define RCC_PLL3DIVR1_DIVN_2 (0x004UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000004 */15364 #define RCC_PLL3DIVR1_DIVN_3 (0x008UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000008 */15365 #define RCC_PLL3DIVR1_DIVN_4 (0x010UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000010 */15366 #define RCC_PLL3DIVR1_DIVN_5 (0x020UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000020 */15367 #define RCC_PLL3DIVR1_DIVN_6 (0x040UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000040 */15368 #define RCC_PLL3DIVR1_DIVN_7 (0x080UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000080 */[all …]
