Searched refs:RCC_PLL3CFGR3_PLL3PDIV2_Pos (Results 1 – 9 of 9) sorted by relevance
345 pllp2 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos; in SystemCoreClockUpdate()
402 pllp2 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos; in SystemCoreClockUpdate()
25500 #define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24U) macro25501 #define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x070000…
26649 #define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24U) macro26650 #define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x070000…
26407 #define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24U) macro26408 #define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x070000…
25742 #define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24U) macro25743 #define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x070000…
1728 …scInitStruct->PLL3.PLLP2 = ((cfgr_value & RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos); in HAL_RCC_GetOscConfig()
5938 MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV2, P2 << RCC_PLL3CFGR3_PLL3PDIV2_Pos); in LL_RCC_PLL3_SetP2()5948 …eturn (uint32_t)(READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos); in LL_RCC_PLL3_GetP2()
3848 ((((__PLLP2__) << RCC_PLL3CFGR3_PLL3PDIV2_Pos) & RCC_PLL3CFGR3_PLL3PDIV2)))); \