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Searched refs:RCC_PLL3CFGR3_PLL3PDIV1_Pos (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c344 pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos; in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c401 pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos; in SystemCoreClockUpdate()
Dstm32n645xx.h25503 #define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27U) macro
25504 #define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x380000…
Dstm32n657xx.h26652 #define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27U) macro
26653 #define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x380000…
Dstm32n655xx.h26410 #define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27U) macro
26411 #define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x380000…
Dstm32n647xx.h25745 #define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27U) macro
25746 #define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x380000…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c1727 …scInitStruct->PLL3.PLLP1 = ((cfgr_value & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h5917 MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV1, P1 << RCC_PLL3CFGR3_PLL3PDIV1_Pos); in LL_RCC_PLL3_SetP1()
5927 …eturn (uint32_t)(READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos); in LL_RCC_PLL3_GetP1()
Dstm32n6xx_hal_rcc.h3847 ((((__PLLP1__) << RCC_PLL3CFGR3_PLL3PDIV1_Pos) & RCC_PLL3CFGR3_PLL3PDIV1) | \