Searched refs:RCC_PLL3CFGR3_PLL3PDIV1_Pos (Results 1 – 9 of 9) sorted by relevance
344 pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos; in SystemCoreClockUpdate()
401 pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos; in SystemCoreClockUpdate()
25503 #define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27U) macro25504 #define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x380000…
26652 #define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27U) macro26653 #define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x380000…
26410 #define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27U) macro26411 #define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x380000…
25745 #define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27U) macro25746 #define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x380000…
1727 …scInitStruct->PLL3.PLLP1 = ((cfgr_value & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos); in HAL_RCC_GetOscConfig()
5917 MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV1, P1 << RCC_PLL3CFGR3_PLL3PDIV1_Pos); in LL_RCC_PLL3_SetP1()5927 …eturn (uint32_t)(READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos); in LL_RCC_PLL3_GetP1()
3847 ((((__PLLP1__) << RCC_PLL3CFGR3_PLL3PDIV1_Pos) & RCC_PLL3CFGR3_PLL3PDIV1) | \