Home
last modified time | relevance | path

Searched refs:RCC_PLL3CFGR2_DIVR (Results 1 – 25 of 27) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_rcc.c1865 …RCC_OscInitStruct->PLL3.PLLR = (uint32_t)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVR) >> RCC_PLL3CFGR2_D… in HAL_RCC_GetOscConfig()
2142 …LL3_R_Frequency = (uint32_t)(pll3vco / ((float)(((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVR) >> RCC_PLL3… in HAL_RCC_GetPLL3ClockFreq()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_rcc.h4739 return (uint32_t)((READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_DIVR) >> RCC_PLL3CFGR2_DIVR_Pos) + 1U); in LL_RCC_PLL3_GetR()
4815 MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_DIVR, (DIVR - 1U) << RCC_PLL3CFGR2_DIVR_Pos); in LL_RCC_PLL3_SetR()
Dstm32mp1xx_hal_rcc.h3535 … MODIFY_REG( RCC->PLL3CFGR2, (RCC_PLL3CFGR2_DIVP | RCC_PLL3CFGR2_DIVQ | RCC_PLL3CFGR2_DIVR), \
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h25312 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp151fxx_cm4.h25475 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp151axx_ca7.h25312 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp151axx_cm4.h25278 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp151dxx_cm4.h25278 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp151cxx_ca7.h25509 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp151cxx_cm4.h25475 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp151fxx_ca7.h25509 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp153axx_ca7.h26863 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp153axx_cm4.h26829 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp153cxx_ca7.h27060 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp153cxx_cm4.h27026 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp153dxx_ca7.h26863 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp153dxx_cm4.h26829 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp153fxx_ca7.h27060 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp153fxx_cm4.h27026 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp157axx_ca7.h28086 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp157axx_cm4.h28052 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp157cxx_ca7.h28283 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp157cxx_cm4.h28249 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp157dxx_ca7.h28086 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro
Dstm32mp157dxx_cm4.h28052 #define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk … macro

12