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Searched refs:RCC_PLL3CFGR1_PLL3DIVN_Pos (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c341 plln = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos; in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c398 plln = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos; in SystemCoreClockUpdate()
Dstm32n645xx.h25457 #define RCC_PLL3CFGR1_PLL3DIVN_Pos (8U) macro
25458 #define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000F…
Dstm32n657xx.h26606 #define RCC_PLL3CFGR1_PLL3DIVN_Pos (8U) macro
26607 #define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000F…
Dstm32n655xx.h26364 #define RCC_PLL3CFGR1_PLL3DIVN_Pos (8U) macro
26365 #define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000F…
Dstm32n647xx.h25699 #define RCC_PLL3CFGR1_PLL3DIVN_Pos (8U) macro
25700 #define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000F…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c1723 …C_OscInitStruct->PLL3.PLLN = ((cfgr_value & RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h5874 MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVN, N << RCC_PLL3CFGR1_PLL3DIVN_Pos); in LL_RCC_PLL3_SetN()
5885 …return (uint32_t)((READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos)… in LL_RCC_PLL3_GetN()
Dstm32n6xx_hal_rcc.h3844 … | ( (__PLLM__) << RCC_PLL3CFGR1_PLL3DIVM_Pos) | (((__PLLN__) << RCC_PLL3CFGR1_PLL3DIVN_Pos)))); \