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Searched refs:RCC_PLL3CFGR1_PLL3DIVM_Pos (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c340 pllm = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos; in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c397 pllm = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos; in SystemCoreClockUpdate()
Dstm32n645xx.h25460 #define RCC_PLL3CFGR1_PLL3DIVM_Pos (20U) macro
25461 #define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F000…
Dstm32n657xx.h26609 #define RCC_PLL3CFGR1_PLL3DIVM_Pos (20U) macro
26610 #define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F000…
Dstm32n655xx.h26367 #define RCC_PLL3CFGR1_PLL3DIVM_Pos (20U) macro
26368 #define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F000…
Dstm32n647xx.h25702 #define RCC_PLL3CFGR1_PLL3DIVM_Pos (20U) macro
25703 #define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F000…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c1722 …C_OscInitStruct->PLL3.PLLM = ((cfgr_value & RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h5896 MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVM, M << RCC_PLL3CFGR1_PLL3DIVM_Pos); in LL_RCC_PLL3_SetM()
5906 return (uint32_t)(READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos); in LL_RCC_PLL3_GetM()
Dstm32n6xx_hal_rcc.h3844 …((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL3CFGR1_PLL3DIVM_Pos) | (((__PLLN__) << RCC_PLL3CFGR1_PLL…