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Searched refs:RCC_PLL2DIVR_N2_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h4825 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1UL); in LL_RCC_PLL2_GetN()
4886 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N - 1UL) << RCC_PLL2DIVR_N2_Pos); in LL_RCC_PLL2_SetN()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_rcc_ex.h1466 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, ((__PLL2N__) - 1U) << RCC_PLL2DIVR_N2_Pos)
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc_ex.c1752 …PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) +… in HAL_RCCEx_GetPeriphCLKConfig()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h13144 #define RCC_PLL2DIVR_N2_Pos (0U) macro
13145 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h7b0xx.h13588 #define RCC_PLL2DIVR_N2_Pos (0U) macro
13589 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h7b0xxq.h13600 #define RCC_PLL2DIVR_N2_Pos (0U) macro
13601 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h7a3xxq.h13156 #define RCC_PLL2DIVR_N2_Pos (0U) macro
13157 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h7b3xx.h13595 #define RCC_PLL2DIVR_N2_Pos (0U) macro
13596 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h7b3xxq.h13607 #define RCC_PLL2DIVR_N2_Pos (0U) macro
13608 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h730xxq.h15456 #define RCC_PLL2DIVR_N2_Pos (0U) macro
15457 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h733xx.h15444 #define RCC_PLL2DIVR_N2_Pos (0U) macro
15445 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h725xx.h15005 #define RCC_PLL2DIVR_N2_Pos (0U) macro
15006 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h730xx.h15444 #define RCC_PLL2DIVR_N2_Pos (0U) macro
15445 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h735xx.h15456 #define RCC_PLL2DIVR_N2_Pos (0U) macro
15457 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h742xx.h14330 #define RCC_PLL2DIVR_N2_Pos (0U) macro
14331 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h723xx.h14993 #define RCC_PLL2DIVR_N2_Pos (0U) macro
14994 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h750xx.h15223 #define RCC_PLL2DIVR_N2_Pos (0U) macro
15224 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h753xx.h15229 #define RCC_PLL2DIVR_N2_Pos (0U) macro
15230 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h745xx.h15536 #define RCC_PLL2DIVR_N2_Pos (0U) macro
15537 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h745xg.h15536 #define RCC_PLL2DIVR_N2_Pos (0U) macro
15537 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h743xx.h14960 #define RCC_PLL2DIVR_N2_Pos (0U) macro
14961 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h755xx.h15805 #define RCC_PLL2DIVR_N2_Pos (0U) macro
15806 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h757xx.h18962 #define RCC_PLL2DIVR_N2_Pos (0U) macro
18963 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h747xg.h18693 #define RCC_PLL2DIVR_N2_Pos (0U) macro
18694 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
Dstm32h747xx.h18693 #define RCC_PLL2DIVR_N2_Pos (0U) macro
18694 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */