Searched refs:RCC_PLL2DIVR1_DIVR_Pos (Results 1 – 7 of 7) sorted by relevance
1551 pllr = ((RCC->PLL2DIVR1 & RCC_PLL2DIVR1_DIVR) >> RCC_PLL2DIVR1_DIVR_Pos) + 1U; in HAL_RCC_GetPLL2RFreq()1771 RCC_OscInitStruct->PLL2.PLLR = (((regvalue & RCC_PLL2DIVR1_DIVR) >> RCC_PLL2DIVR1_DIVR_Pos) + 1U); in HAL_RCC_GetOscConfig()
4537 …return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVR) >> RCC_PLL2DIVR1_DIVR_Pos) + 1UL); in LL_RCC_PLL2_GetR()4622 MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVR, (R - 1UL) << RCC_PLL2DIVR1_DIVR_Pos); in LL_RCC_PLL2_SetR()
4088 … ((((__PLL2R__) - 1U) << RCC_PLL2DIVR1_DIVR_Pos) & RCC_PLL2DIVR1_DIVR))); \
14941 #define RCC_PLL2DIVR1_DIVR_Pos (24U) macro14942 #define RCC_PLL2DIVR1_DIVR_Msk (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x7F000000 */14944 #define RCC_PLL2DIVR1_DIVR_0 (0x001UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x01000000 */14945 #define RCC_PLL2DIVR1_DIVR_1 (0x002UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x02000000 */14946 #define RCC_PLL2DIVR1_DIVR_2 (0x004UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x04000000 */14947 #define RCC_PLL2DIVR1_DIVR_3 (0x008UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x08000000 */14948 #define RCC_PLL2DIVR1_DIVR_4 (0x010UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x10000000 */14949 #define RCC_PLL2DIVR1_DIVR_5 (0x020UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x20000000 */14950 #define RCC_PLL2DIVR1_DIVR_6 (0x040UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x40000000 */
15975 #define RCC_PLL2DIVR1_DIVR_Pos (24U) macro15976 #define RCC_PLL2DIVR1_DIVR_Msk (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x7F000000 */15978 #define RCC_PLL2DIVR1_DIVR_0 (0x001UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x01000000 */15979 #define RCC_PLL2DIVR1_DIVR_1 (0x002UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x02000000 */15980 #define RCC_PLL2DIVR1_DIVR_2 (0x004UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x04000000 */15981 #define RCC_PLL2DIVR1_DIVR_3 (0x008UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x08000000 */15982 #define RCC_PLL2DIVR1_DIVR_4 (0x010UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x10000000 */15983 #define RCC_PLL2DIVR1_DIVR_5 (0x020UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x20000000 */15984 #define RCC_PLL2DIVR1_DIVR_6 (0x040UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x40000000 */
15573 #define RCC_PLL2DIVR1_DIVR_Pos (24U) macro15574 #define RCC_PLL2DIVR1_DIVR_Msk (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x7F000000 */15576 #define RCC_PLL2DIVR1_DIVR_0 (0x001UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x01000000 */15577 #define RCC_PLL2DIVR1_DIVR_1 (0x002UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x02000000 */15578 #define RCC_PLL2DIVR1_DIVR_2 (0x004UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x04000000 */15579 #define RCC_PLL2DIVR1_DIVR_3 (0x008UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x08000000 */15580 #define RCC_PLL2DIVR1_DIVR_4 (0x010UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x10000000 */15581 #define RCC_PLL2DIVR1_DIVR_5 (0x020UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x20000000 */15582 #define RCC_PLL2DIVR1_DIVR_6 (0x040UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x40000000 */
15341 #define RCC_PLL2DIVR1_DIVR_Pos (24U) macro15342 #define RCC_PLL2DIVR1_DIVR_Msk (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x7F000000 */15344 #define RCC_PLL2DIVR1_DIVR_0 (0x001UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x01000000 */15345 #define RCC_PLL2DIVR1_DIVR_1 (0x002UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x02000000 */15346 #define RCC_PLL2DIVR1_DIVR_2 (0x004UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x04000000 */15347 #define RCC_PLL2DIVR1_DIVR_3 (0x008UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x08000000 */15348 #define RCC_PLL2DIVR1_DIVR_4 (0x010UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x10000000 */15349 #define RCC_PLL2DIVR1_DIVR_5 (0x020UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x20000000 */15350 #define RCC_PLL2DIVR1_DIVR_6 (0x040UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x40000000 */
