Searched refs:RCC_PLL2DIVR1_DIVQ_Pos (Results 1 – 7 of 7) sorted by relevance
1536 pllq = ((RCC->PLL2DIVR1 & RCC_PLL2DIVR1_DIVQ) >> RCC_PLL2DIVR1_DIVQ_Pos) + 1U; in HAL_RCC_GetPLL2QFreq()1773 RCC_OscInitStruct->PLL2.PLLQ = (((regvalue & RCC_PLL2DIVR1_DIVQ) >> RCC_PLL2DIVR1_DIVQ_Pos) + 1U); in HAL_RCC_GetOscConfig()
4527 …return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVQ) >> RCC_PLL2DIVR1_DIVQ_Pos) + 1UL); in LL_RCC_PLL2_GetQ()4611 MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVQ, (Q - 1UL) << RCC_PLL2DIVR1_DIVQ_Pos); in LL_RCC_PLL2_SetQ()
4087 … ((((__PLL2Q__) - 1U) << RCC_PLL2DIVR1_DIVQ_Pos) & RCC_PLL2DIVR1_DIVQ) | \
14930 #define RCC_PLL2DIVR1_DIVQ_Pos (16U) macro14931 #define RCC_PLL2DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x007F0000 */14933 #define RCC_PLL2DIVR1_DIVQ_0 (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00010000 */14934 #define RCC_PLL2DIVR1_DIVQ_1 (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00020000 */14935 #define RCC_PLL2DIVR1_DIVQ_2 (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00040000 */14936 #define RCC_PLL2DIVR1_DIVQ_3 (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00080000 */14937 #define RCC_PLL2DIVR1_DIVQ_4 (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00100000 */14938 #define RCC_PLL2DIVR1_DIVQ_5 (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00200000 */14939 #define RCC_PLL2DIVR1_DIVQ_6 (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00400000 */
15964 #define RCC_PLL2DIVR1_DIVQ_Pos (16U) macro15965 #define RCC_PLL2DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x007F0000 */15967 #define RCC_PLL2DIVR1_DIVQ_0 (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00010000 */15968 #define RCC_PLL2DIVR1_DIVQ_1 (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00020000 */15969 #define RCC_PLL2DIVR1_DIVQ_2 (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00040000 */15970 #define RCC_PLL2DIVR1_DIVQ_3 (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00080000 */15971 #define RCC_PLL2DIVR1_DIVQ_4 (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00100000 */15972 #define RCC_PLL2DIVR1_DIVQ_5 (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00200000 */15973 #define RCC_PLL2DIVR1_DIVQ_6 (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00400000 */
15562 #define RCC_PLL2DIVR1_DIVQ_Pos (16U) macro15563 #define RCC_PLL2DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x007F0000 */15565 #define RCC_PLL2DIVR1_DIVQ_0 (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00010000 */15566 #define RCC_PLL2DIVR1_DIVQ_1 (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00020000 */15567 #define RCC_PLL2DIVR1_DIVQ_2 (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00040000 */15568 #define RCC_PLL2DIVR1_DIVQ_3 (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00080000 */15569 #define RCC_PLL2DIVR1_DIVQ_4 (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00100000 */15570 #define RCC_PLL2DIVR1_DIVQ_5 (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00200000 */15571 #define RCC_PLL2DIVR1_DIVQ_6 (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00400000 */
15330 #define RCC_PLL2DIVR1_DIVQ_Pos (16U) macro15331 #define RCC_PLL2DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x007F0000 */15333 #define RCC_PLL2DIVR1_DIVQ_0 (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00010000 */15334 #define RCC_PLL2DIVR1_DIVQ_1 (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00020000 */15335 #define RCC_PLL2DIVR1_DIVQ_2 (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00040000 */15336 #define RCC_PLL2DIVR1_DIVQ_3 (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00080000 */15337 #define RCC_PLL2DIVR1_DIVQ_4 (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00100000 */15338 #define RCC_PLL2DIVR1_DIVQ_5 (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00200000 */15339 #define RCC_PLL2DIVR1_DIVQ_6 (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00400000 */
