Searched refs:RCC_PLL2DIVR1_DIVP_Pos (Results 1 – 7 of 7) sorted by relevance
1521 pllp = ((RCC->PLL2DIVR1 & RCC_PLL2DIVR1_DIVP) >> RCC_PLL2DIVR1_DIVP_Pos) + 1U; in HAL_RCC_GetPLL2PFreq()1772 RCC_OscInitStruct->PLL2.PLLP = (((regvalue & RCC_PLL2DIVR1_DIVP) >> RCC_PLL2DIVR1_DIVP_Pos) + 1U); in HAL_RCC_GetOscConfig()
4517 …return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVP) >> RCC_PLL2DIVR1_DIVP_Pos) + 1UL); in LL_RCC_PLL2_GetP()4600 MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVP, (P - 1UL) << RCC_PLL2DIVR1_DIVP_Pos); in LL_RCC_PLL2_SetP()
4086 … ((((__PLL2P__) - 1U) << RCC_PLL2DIVR1_DIVP_Pos) & RCC_PLL2DIVR1_DIVP) | \
14919 #define RCC_PLL2DIVR1_DIVP_Pos (9U) macro14920 #define RCC_PLL2DIVR1_DIVP_Msk (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x0000FE00 */14922 #define RCC_PLL2DIVR1_DIVP_0 (0x001UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000200 */14923 #define RCC_PLL2DIVR1_DIVP_1 (0x002UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000400 */14924 #define RCC_PLL2DIVR1_DIVP_2 (0x004UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000800 */14925 #define RCC_PLL2DIVR1_DIVP_3 (0x008UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00001000 */14926 #define RCC_PLL2DIVR1_DIVP_4 (0x010UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00002000 */14927 #define RCC_PLL2DIVR1_DIVP_5 (0x020UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00004000 */14928 #define RCC_PLL2DIVR1_DIVP_6 (0x040UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00008000 */
15953 #define RCC_PLL2DIVR1_DIVP_Pos (9U) macro15954 #define RCC_PLL2DIVR1_DIVP_Msk (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x0000FE00 */15956 #define RCC_PLL2DIVR1_DIVP_0 (0x001UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000200 */15957 #define RCC_PLL2DIVR1_DIVP_1 (0x002UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000400 */15958 #define RCC_PLL2DIVR1_DIVP_2 (0x004UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000800 */15959 #define RCC_PLL2DIVR1_DIVP_3 (0x008UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00001000 */15960 #define RCC_PLL2DIVR1_DIVP_4 (0x010UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00002000 */15961 #define RCC_PLL2DIVR1_DIVP_5 (0x020UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00004000 */15962 #define RCC_PLL2DIVR1_DIVP_6 (0x040UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00008000 */
15551 #define RCC_PLL2DIVR1_DIVP_Pos (9U) macro15552 #define RCC_PLL2DIVR1_DIVP_Msk (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x0000FE00 */15554 #define RCC_PLL2DIVR1_DIVP_0 (0x001UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000200 */15555 #define RCC_PLL2DIVR1_DIVP_1 (0x002UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000400 */15556 #define RCC_PLL2DIVR1_DIVP_2 (0x004UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000800 */15557 #define RCC_PLL2DIVR1_DIVP_3 (0x008UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00001000 */15558 #define RCC_PLL2DIVR1_DIVP_4 (0x010UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00002000 */15559 #define RCC_PLL2DIVR1_DIVP_5 (0x020UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00004000 */15560 #define RCC_PLL2DIVR1_DIVP_6 (0x040UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00008000 */
15319 #define RCC_PLL2DIVR1_DIVP_Pos (9U) macro15320 #define RCC_PLL2DIVR1_DIVP_Msk (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x0000FE00 */15322 #define RCC_PLL2DIVR1_DIVP_0 (0x001UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000200 */15323 #define RCC_PLL2DIVR1_DIVP_1 (0x002UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000400 */15324 #define RCC_PLL2DIVR1_DIVP_2 (0x004UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000800 */15325 #define RCC_PLL2DIVR1_DIVP_3 (0x008UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00001000 */15326 #define RCC_PLL2DIVR1_DIVP_4 (0x010UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00002000 */15327 #define RCC_PLL2DIVR1_DIVP_5 (0x020UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00004000 */15328 #define RCC_PLL2DIVR1_DIVP_6 (0x040UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00008000 */
