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Searched refs:RCC_PLL2CFGR3_PLL2PDIV1_Pos (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c329 pllp1 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos; in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c386 pllp1 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos; in SystemCoreClockUpdate()
Dstm32n645xx.h25449 #define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27U) macro
25450 #define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x380000…
Dstm32n657xx.h26598 #define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27U) macro
26599 #define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x380000…
Dstm32n655xx.h26356 #define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27U) macro
26357 #define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x380000…
Dstm32n647xx.h25691 #define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27U) macro
25692 #define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x380000…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c1700 …scInitStruct->PLL2.PLLP1 = ((cfgr_value & RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h5567 MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV1, P1 << RCC_PLL2CFGR3_PLL2PDIV1_Pos); in LL_RCC_PLL2_SetP1()
5577 …eturn (uint32_t)(READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos); in LL_RCC_PLL2_GetP1()
Dstm32n6xx_hal_rcc.h3744 ((((__PLLP1__) << RCC_PLL2CFGR3_PLL2PDIV1_Pos) & RCC_PLL2CFGR3_PLL2PDIV1) | \