Home
last modified time | relevance | path

Searched refs:RCC_PLL1DIVR_R1_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc.c866 …((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLL… in HAL_RCC_OscConfig()
1702 …RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)… in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h4551 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL); in LL_RCC_PLL1_GetR()
4618 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos); in LL_RCC_PLL1_SetR()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h13134 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13135 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h7b0xx.h13578 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13579 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h7b0xxq.h13590 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13591 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h7a3xxq.h13146 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13147 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h7b3xx.h13585 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13586 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h7b3xxq.h13597 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13598 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h730xxq.h15446 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15447 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h733xx.h15434 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15435 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h725xx.h14995 #define RCC_PLL1DIVR_R1_Pos (24U) macro
14996 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h730xx.h15434 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15435 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h735xx.h15446 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15447 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h742xx.h14320 #define RCC_PLL1DIVR_R1_Pos (24U) macro
14321 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h723xx.h14983 #define RCC_PLL1DIVR_R1_Pos (24U) macro
14984 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h750xx.h15213 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15214 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h753xx.h15219 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15220 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h745xx.h15526 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15527 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h745xg.h15526 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15527 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h743xx.h14950 #define RCC_PLL1DIVR_R1_Pos (24U) macro
14951 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h755xx.h15795 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15796 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h757xx.h18952 #define RCC_PLL1DIVR_R1_Pos (24U) macro
18953 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h747xg.h18683 #define RCC_PLL1DIVR_R1_Pos (24U) macro
18684 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h747xx.h18683 #define RCC_PLL1DIVR_R1_Pos (24U) macro
18684 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */