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Searched refs:RCC_PLL1DIVR_Q1_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc.c865 …((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLL… in HAL_RCC_OscConfig()
1704 …RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos)… in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h4541 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1UL); in LL_RCC_PLL1_GetQ()
4607 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q - 1UL) << RCC_PLL1DIVR_Q1_Pos); in LL_RCC_PLL1_SetQ()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h13131 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
13132 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h7b0xx.h13575 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
13576 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h7b0xxq.h13587 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
13588 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h7a3xxq.h13143 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
13144 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h7b3xx.h13582 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
13583 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h7b3xxq.h13594 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
13595 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h730xxq.h15443 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
15444 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h733xx.h15431 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
15432 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h725xx.h14992 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
14993 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h730xx.h15431 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
15432 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h735xx.h15443 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
15444 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h742xx.h14317 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
14318 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h723xx.h14980 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
14981 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h750xx.h15210 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
15211 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h753xx.h15216 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
15217 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h745xx.h15523 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
15524 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h745xg.h15523 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
15524 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h743xx.h14947 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
14948 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h755xx.h15792 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
15793 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h757xx.h18949 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
18950 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h747xg.h18680 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
18681 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
Dstm32h747xx.h18680 #define RCC_PLL1DIVR_Q1_Pos (16U) macro
18681 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */