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Searched refs:RCC_PLL1DIVR_Q1_Msk (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h13132 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
13133 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h7b0xx.h13576 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
13577 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h7b0xxq.h13588 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
13589 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h7a3xxq.h13144 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
13145 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h7b3xx.h13583 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
13584 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h7b3xxq.h13595 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
13596 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h730xxq.h15444 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
15445 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h733xx.h15432 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
15433 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h725xx.h14993 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
14994 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h730xx.h15432 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
15433 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h735xx.h15444 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
15445 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h742xx.h14318 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
14319 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h723xx.h14981 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
14982 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h750xx.h15211 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
15212 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h753xx.h15217 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
15218 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h745xx.h15524 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
15525 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h745xg.h15524 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
15525 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h743xx.h14948 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
14949 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h755xx.h15793 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
15794 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h757xx.h18950 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
18951 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h747xg.h18681 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
18682 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
Dstm32h747xx.h18681 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */ macro
18682 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk