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Searched refs:RCC_PLL1DIVR_PLL1P_Pos (Results 1 – 25 of 36) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_rcc.c817 ((RCC_OscInitStruct->PLL1.PLLP - 1u) << RCC_PLL1DIVR_PLL1P_Pos) | in HAL_RCC_OscConfig()
886 …(((tmpreg2 & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) != (RCC_OscInitStruct->PLL1.PLLP - 1u)… in HAL_RCC_OscConfig()
1395 pllp = ((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U; in HAL_RCC_GetPLL1PFreq()
1507 RCC_OscInitStruct->PLL1.PLLP = (((regvalue & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc.c958 RCC_PLL1DIVR_PLL1P_Pos) != (pOscInitStruct->PLL.PLLP - 1U)) || in HAL_RCC_OscConfig()
1470 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U) ; in HAL_RCC_GetSysClockFreq()
1609 …pOscInitStruct->PLL.PLLP = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) +… in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h2334 …L1DIVR_PLL1P, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << RCC_PLL1DIVR_PLL1P_Pos)); in LL_RCC_PLL1_ConfigDomain_PLL1P()
2416 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos); in LL_RCC_PLL1_SetP()
2427 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL); in LL_RCC_PLL1_GetP()
Dstm32wbaxx_hal_rcc.h2027 …WRITE_REG(RCC->PLL1DIVR, (((__PLL1N__) - 1U) | (((__PLL1P__) - 1U) << RCC_PLL1DIVR_PLL1P_Pos) | ((…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dsystem_stm32h5xx.c373 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ; in SystemCoreClockUpdate()
Dsystem_stm32h5xx_s.c387 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ; in SystemCoreClockUpdate()
Dstm32h503xx.h8569 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
8570 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
8572 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
8573 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
8574 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
8575 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
8576 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
8577 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
8578 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32h523xx.h12745 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
12746 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
12748 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
12749 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
12750 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
12751 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
12752 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
12753 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
12754 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32h562xx.h13425 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
13426 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
13428 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
13429 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
13430 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
13431 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
13432 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
13433 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
13434 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32h533xx.h13264 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
13265 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
13267 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
13268 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
13269 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
13270 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
13271 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
13272 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
13273 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32h573xx.h16028 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
16029 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
16031 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
16032 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
16033 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
16034 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
16035 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
16036 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
16037 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32h563xx.h15509 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
15510 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
15512 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
15513 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
15514 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
15515 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
15516 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
15517 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
15518 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc.c1279 RCC_PLL1DIVR_PLL1P_Pos) != (pRCC_OscInitStruct->PLL.PLLP - 1U)) || in HAL_RCC_OscConfig()
1945 …InitStruct->PLL.PLLP = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U); in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h4331 ((PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos)); in LL_RCC_PLL1_ConfigDomain_SYS()
4391 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos); in LL_RCC_PLL1_SetP()
4402 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL); in LL_RCC_PLL1_GetP()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h3924 RCC_PLL1DIVR_PLL1P_Pos)); in LL_RCC_PLL1_ConfigDomain_SAI()
4017 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos); in LL_RCC_PLL1_SetP()
4029 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL); in LL_RCC_PLL1_GetP()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h6041 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
6042 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
6044 #define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
6045 #define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
6046 #define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
6047 #define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
6048 #define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
6049 #define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
6050 #define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32wba52xx.h9815 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
9816 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
9818 #define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
9819 #define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
9820 #define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
9821 #define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
9822 #define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
9823 #define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
9824 #define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32wba54xx.h10087 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
10088 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
10090 #define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
10091 #define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
10092 #define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
10093 #define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
10094 #define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
10095 #define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
10096 #define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32wba5mxx.h10105 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
10106 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
10108 #define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
10109 #define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
10110 #define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
10111 #define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
10112 #define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
10113 #define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
10114 #define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32wba55xx.h10105 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
10106 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
10108 #define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
10109 #define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
10110 #define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
10111 #define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
10112 #define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
10113 #define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
10114 #define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14585 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
14586 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
14588 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
14589 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
14590 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
14591 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
14592 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
14593 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
14594 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32u535xx.h14072 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
14073 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
14075 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
14076 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
14077 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
14078 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
14079 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
14080 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
14081 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32u575xx.h15480 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
15481 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
15483 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
15484 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
15485 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
15486 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
15487 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
15488 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
15489 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32u585xx.h16042 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
16043 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
16045 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
16046 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
16047 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
16048 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
16049 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
16050 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
16051 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…
Dstm32u595xx.h16508 #define RCC_PLL1DIVR_PLL1P_Pos (9U) macro
16509 #define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00…
16511 #define RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200…
16512 #define RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400…
16513 #define RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800…
16514 #define RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000…
16515 #define RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000…
16516 #define RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000…
16517 #define RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000…

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