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Searched refs:RCC_PLL1DIVR_P1_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc.c864 …((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLL… in HAL_RCC_OscConfig()
1703 …RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos)… in HAL_RCC_GetOscConfig()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h4531 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1UL); in LL_RCC_PLL1_GetP()
4596 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P - 1UL) << RCC_PLL1DIVR_P1_Pos); in LL_RCC_PLL1_SetP()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h13128 #define RCC_PLL1DIVR_P1_Pos (9U) macro
13129 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h7b0xx.h13572 #define RCC_PLL1DIVR_P1_Pos (9U) macro
13573 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h7b0xxq.h13584 #define RCC_PLL1DIVR_P1_Pos (9U) macro
13585 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h7a3xxq.h13140 #define RCC_PLL1DIVR_P1_Pos (9U) macro
13141 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h7b3xx.h13579 #define RCC_PLL1DIVR_P1_Pos (9U) macro
13580 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h7b3xxq.h13591 #define RCC_PLL1DIVR_P1_Pos (9U) macro
13592 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h730xxq.h15440 #define RCC_PLL1DIVR_P1_Pos (9U) macro
15441 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h733xx.h15428 #define RCC_PLL1DIVR_P1_Pos (9U) macro
15429 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h725xx.h14989 #define RCC_PLL1DIVR_P1_Pos (9U) macro
14990 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h730xx.h15428 #define RCC_PLL1DIVR_P1_Pos (9U) macro
15429 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h735xx.h15440 #define RCC_PLL1DIVR_P1_Pos (9U) macro
15441 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h742xx.h14314 #define RCC_PLL1DIVR_P1_Pos (9U) macro
14315 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h723xx.h14977 #define RCC_PLL1DIVR_P1_Pos (9U) macro
14978 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h750xx.h15207 #define RCC_PLL1DIVR_P1_Pos (9U) macro
15208 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h753xx.h15213 #define RCC_PLL1DIVR_P1_Pos (9U) macro
15214 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h745xx.h15520 #define RCC_PLL1DIVR_P1_Pos (9U) macro
15521 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h745xg.h15520 #define RCC_PLL1DIVR_P1_Pos (9U) macro
15521 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h743xx.h14944 #define RCC_PLL1DIVR_P1_Pos (9U) macro
14945 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h755xx.h15789 #define RCC_PLL1DIVR_P1_Pos (9U) macro
15790 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h757xx.h18946 #define RCC_PLL1DIVR_P1_Pos (9U) macro
18947 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h747xg.h18677 #define RCC_PLL1DIVR_P1_Pos (9U) macro
18678 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
Dstm32h747xx.h18677 #define RCC_PLL1DIVR_P1_Pos (9U) macro
18678 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */