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Searched refs:RCC_PLL1DIVR_P1 (Results 1 – 25 of 32) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc.c864 …((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLL… in HAL_RCC_OscConfig()
1458 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; in HAL_RCC_GetSysClockFreq()
1703 …RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos)… in HAL_RCC_GetOscConfig()
Dstm32h7xx_hal_rcc_ex.c3122 … (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (fl… in HAL_RCCEx_GetPLL1ClockFreq()
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dsystem_stm32h7xx.c397 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dsystem_stm32h7xx_dualcore_bootcm4_cm7gated.c376 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; in SystemCoreClockUpdate()
Dsystem_stm32h7xx_dualcore_bootcm7_cm4gated.c382 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; in SystemCoreClockUpdate()
Dsystem_stm32h7xx_dualcore_boot_cm4_cm7.c384 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; in SystemCoreClockUpdate()
Dsystem_stm32h7xx_singlecore.c377 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; in SystemCoreClockUpdate()
Dsystem_stm32h7xx.c402 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; in SystemCoreClockUpdate()
Dstm32h7a3xx.h13130 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h7b0xx.h13574 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h7b0xxq.h13586 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h7a3xxq.h13142 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h7b3xx.h13581 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h7b3xxq.h13593 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h730xxq.h15442 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h733xx.h15430 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h725xx.h14991 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h730xx.h15430 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h735xx.h15442 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h742xx.h14316 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h723xx.h14979 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h750xx.h15209 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
Dstm32h753xx.h15215 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk macro
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h4531 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1UL); in LL_RCC_PLL1_GetP()
4596 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P - 1UL) << RCC_PLL1DIVR_P1_Pos); in LL_RCC_PLL1_SetP()
Dstm32h7xx_hal_rcc.h7593 …IVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \

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