Searched refs:RCC_PLL1DIVR1_DIVQ_Pos (Results 1 – 7 of 7) sorted by relevance
1476 pllq = ((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1U; in HAL_RCC_GetPLL1QFreq()1734 RCC_OscInitStruct->PLL1.PLLQ = (((regvalue & RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1U); in HAL_RCC_GetOscConfig()2041 ((pPLLInit->PLLQ - 1U) << RCC_PLL1DIVR1_DIVQ_Pos) | in RCC_PLL_Config()
4021 …return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1UL); in LL_RCC_PLL1_GetQ()4095 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVQ, (Q - 1UL) << RCC_PLL1DIVR1_DIVQ_Pos); in LL_RCC_PLL1_SetQ()
3947 … ((((__PLL1Q__) - 1U) << RCC_PLL1DIVR1_DIVQ_Pos) & RCC_PLL1DIVR1_DIVQ) | \
14878 #define RCC_PLL1DIVR1_DIVQ_Pos (16U) macro14879 #define RCC_PLL1DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x007F0000 */14881 #define RCC_PLL1DIVR1_DIVQ_0 (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00010000 */14882 #define RCC_PLL1DIVR1_DIVQ_1 (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00020000 */14883 #define RCC_PLL1DIVR1_DIVQ_2 (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00040000 */14884 #define RCC_PLL1DIVR1_DIVQ_3 (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00080000 */14885 #define RCC_PLL1DIVR1_DIVQ_4 (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00100000 */14886 #define RCC_PLL1DIVR1_DIVQ_5 (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00200000 */14887 #define RCC_PLL1DIVR1_DIVQ_6 (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00400000 */
15912 #define RCC_PLL1DIVR1_DIVQ_Pos (16U) macro15913 #define RCC_PLL1DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x007F0000 */15915 #define RCC_PLL1DIVR1_DIVQ_0 (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00010000 */15916 #define RCC_PLL1DIVR1_DIVQ_1 (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00020000 */15917 #define RCC_PLL1DIVR1_DIVQ_2 (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00040000 */15918 #define RCC_PLL1DIVR1_DIVQ_3 (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00080000 */15919 #define RCC_PLL1DIVR1_DIVQ_4 (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00100000 */15920 #define RCC_PLL1DIVR1_DIVQ_5 (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00200000 */15921 #define RCC_PLL1DIVR1_DIVQ_6 (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00400000 */
15510 #define RCC_PLL1DIVR1_DIVQ_Pos (16U) macro15511 #define RCC_PLL1DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x007F0000 */15513 #define RCC_PLL1DIVR1_DIVQ_0 (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00010000 */15514 #define RCC_PLL1DIVR1_DIVQ_1 (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00020000 */15515 #define RCC_PLL1DIVR1_DIVQ_2 (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00040000 */15516 #define RCC_PLL1DIVR1_DIVQ_3 (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00080000 */15517 #define RCC_PLL1DIVR1_DIVQ_4 (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00100000 */15518 #define RCC_PLL1DIVR1_DIVQ_5 (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00200000 */15519 #define RCC_PLL1DIVR1_DIVQ_6 (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00400000 */
15278 #define RCC_PLL1DIVR1_DIVQ_Pos (16U) macro15279 #define RCC_PLL1DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x007F0000 */15281 #define RCC_PLL1DIVR1_DIVQ_0 (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00010000 */15282 #define RCC_PLL1DIVR1_DIVQ_1 (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00020000 */15283 #define RCC_PLL1DIVR1_DIVQ_2 (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00040000 */15284 #define RCC_PLL1DIVR1_DIVQ_3 (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00080000 */15285 #define RCC_PLL1DIVR1_DIVQ_4 (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00100000 */15286 #define RCC_PLL1DIVR1_DIVQ_5 (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00200000 */15287 #define RCC_PLL1DIVR1_DIVQ_6 (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00400000 */
