Searched refs:RCC_PLL1DIVR1_DIVQ (Results 1 – 7 of 7) sorted by relevance
1476 pllq = ((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1U; in HAL_RCC_GetPLL1QFreq()1734 RCC_OscInitStruct->PLL1.PLLQ = (((regvalue & RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1U); in HAL_RCC_GetOscConfig()
4021 …return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1UL); in LL_RCC_PLL1_GetQ()4095 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVQ, (Q - 1UL) << RCC_PLL1DIVR1_DIVQ_Pos); in LL_RCC_PLL1_SetQ()
3947 … ((((__PLL1Q__) - 1U) << RCC_PLL1DIVR1_DIVQ_Pos) & RCC_PLL1DIVR1_DIVQ) | \
14880 #define RCC_PLL1DIVR1_DIVQ RCC_PLL1DIVR1_DIVQ_Msk /*!< DIVQ1[6:0] bits: … macro
15914 #define RCC_PLL1DIVR1_DIVQ RCC_PLL1DIVR1_DIVQ_Msk /*!< DIVQ1[6:0] bits: … macro
15512 #define RCC_PLL1DIVR1_DIVQ RCC_PLL1DIVR1_DIVQ_Msk /*!< DIVQ1[6:0] bits: … macro
15280 #define RCC_PLL1DIVR1_DIVQ RCC_PLL1DIVR1_DIVQ_Msk /*!< DIVQ1[6:0] bits: … macro