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Searched refs:RCC_PLL1DIVR1_DIVP_Pos (Results 1 – 8 of 8) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_rcc.c1328 pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U) ; in HAL_RCC_GetSysClockFreq()
1461 pllp = ((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U; in HAL_RCC_GetPLL1PFreq()
1733 RCC_OscInitStruct->PLL1.PLLP = (((regvalue & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U); in HAL_RCC_GetOscConfig()
2040 ((pPLLInit->PLLP - 1U) << RCC_PLL1DIVR1_DIVP_Pos) | in RCC_PLL_Config()
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dsystem_stm32h7rsxx.c248 pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U ) ; in SystemCoreClockUpdate()
Dstm32h7r3xx.h14867 #define RCC_PLL1DIVR1_DIVP_Pos (9U) macro
14868 #define RCC_PLL1DIVR1_DIVP_Msk (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x0000FE00 */
14870 #define RCC_PLL1DIVR1_DIVP_0 (0x001UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000200 */
14871 #define RCC_PLL1DIVR1_DIVP_1 (0x002UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000400 */
14872 #define RCC_PLL1DIVR1_DIVP_2 (0x004UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000800 */
14873 #define RCC_PLL1DIVR1_DIVP_3 (0x008UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00001000 */
14874 #define RCC_PLL1DIVR1_DIVP_4 (0x010UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00002000 */
14875 #define RCC_PLL1DIVR1_DIVP_5 (0x020UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00004000 */
14876 #define RCC_PLL1DIVR1_DIVP_6 (0x040UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00008000 */
Dstm32h7s7xx.h15901 #define RCC_PLL1DIVR1_DIVP_Pos (9U) macro
15902 #define RCC_PLL1DIVR1_DIVP_Msk (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x0000FE00 */
15904 #define RCC_PLL1DIVR1_DIVP_0 (0x001UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000200 */
15905 #define RCC_PLL1DIVR1_DIVP_1 (0x002UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000400 */
15906 #define RCC_PLL1DIVR1_DIVP_2 (0x004UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000800 */
15907 #define RCC_PLL1DIVR1_DIVP_3 (0x008UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00001000 */
15908 #define RCC_PLL1DIVR1_DIVP_4 (0x010UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00002000 */
15909 #define RCC_PLL1DIVR1_DIVP_5 (0x020UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00004000 */
15910 #define RCC_PLL1DIVR1_DIVP_6 (0x040UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00008000 */
Dstm32h7s3xx.h15499 #define RCC_PLL1DIVR1_DIVP_Pos (9U) macro
15500 #define RCC_PLL1DIVR1_DIVP_Msk (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x0000FE00 */
15502 #define RCC_PLL1DIVR1_DIVP_0 (0x001UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000200 */
15503 #define RCC_PLL1DIVR1_DIVP_1 (0x002UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000400 */
15504 #define RCC_PLL1DIVR1_DIVP_2 (0x004UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000800 */
15505 #define RCC_PLL1DIVR1_DIVP_3 (0x008UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00001000 */
15506 #define RCC_PLL1DIVR1_DIVP_4 (0x010UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00002000 */
15507 #define RCC_PLL1DIVR1_DIVP_5 (0x020UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00004000 */
15508 #define RCC_PLL1DIVR1_DIVP_6 (0x040UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00008000 */
Dstm32h7r7xx.h15267 #define RCC_PLL1DIVR1_DIVP_Pos (9U) macro
15268 #define RCC_PLL1DIVR1_DIVP_Msk (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x0000FE00 */
15270 #define RCC_PLL1DIVR1_DIVP_0 (0x001UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000200 */
15271 #define RCC_PLL1DIVR1_DIVP_1 (0x002UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000400 */
15272 #define RCC_PLL1DIVR1_DIVP_2 (0x004UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000800 */
15273 #define RCC_PLL1DIVR1_DIVP_3 (0x008UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00001000 */
15274 #define RCC_PLL1DIVR1_DIVP_4 (0x010UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00002000 */
15275 #define RCC_PLL1DIVR1_DIVP_5 (0x020UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00004000 */
15276 #define RCC_PLL1DIVR1_DIVP_6 (0x040UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_rcc.h3767 ((P - 1UL) << RCC_PLL1DIVR1_DIVP_Pos) | ((N - 1UL) << RCC_PLL1DIVR1_DIVN_Pos)); in LL_RCC_PLL1_ConfigDomain_SYS()
4011 …return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1UL); in LL_RCC_PLL1_GetP()
4084 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP, (P - 1UL) << RCC_PLL1DIVR1_DIVP_Pos); in LL_RCC_PLL1_SetP()
Dstm32h7rsxx_hal_rcc.h3946 … ((((__PLL1P__) - 1U) << RCC_PLL1DIVR1_DIVP_Pos) & RCC_PLL1DIVR1_DIVP) | \