Searched refs:RCC_PLL1DIVR1_DIVP (Results 1 – 8 of 8) sorted by relevance
1328 pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U) ; in HAL_RCC_GetSysClockFreq()1461 pllp = ((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U; in HAL_RCC_GetPLL1PFreq()1733 RCC_OscInitStruct->PLL1.PLLP = (((regvalue & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U); in HAL_RCC_GetOscConfig()
248 pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U ) ; in SystemCoreClockUpdate()
14869 #define RCC_PLL1DIVR1_DIVP RCC_PLL1DIVR1_DIVP_Msk /*!< DIVP1[6:0] bits: … macro
15903 #define RCC_PLL1DIVR1_DIVP RCC_PLL1DIVR1_DIVP_Msk /*!< DIVP1[6:0] bits: … macro
15501 #define RCC_PLL1DIVR1_DIVP RCC_PLL1DIVR1_DIVP_Msk /*!< DIVP1[6:0] bits: … macro
15269 #define RCC_PLL1DIVR1_DIVP RCC_PLL1DIVR1_DIVP_Msk /*!< DIVP1[6:0] bits: … macro
3766 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP | RCC_PLL1DIVR1_DIVN, in LL_RCC_PLL1_ConfigDomain_SYS()4011 …return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1UL); in LL_RCC_PLL1_GetP()4084 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP, (P - 1UL) << RCC_PLL1DIVR1_DIVP_Pos); in LL_RCC_PLL1_SetP()
3946 … ((((__PLL1P__) - 1U) << RCC_PLL1DIVR1_DIVP_Pos) & RCC_PLL1DIVR1_DIVP) | \