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Searched refs:RCC_PLL1CFGR_PLL1REN (Results 1 – 25 of 32) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h2566 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); in LL_RCC_PLL1_EnableDomain_PLL1R()
2580 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); in LL_RCC_PLL1_DisableDomain_PLL1R()
2590 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == RCC_PLL1CFGR_PLL1REN) ? 1UL : 0UL); in LL_RCC_PLL1_IsEnabledDomain_PLL1R()
Dstm32wbaxx_hal_rcc.h265 #define RCC_PLL1_RCLK RCC_PLL1CFGR_PLL1REN
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_rcc.c812 … ((RCC_OscInitStruct->PLL1.PLLM - 1u) << RCC_PLL1CFGR_PLL1M_Pos) | RCC_PLL1CFGR_PLL1REN); in HAL_RCC_OscConfig()
867 RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN)); in HAL_RCC_OscConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h4265 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); in LL_RCC_PLL1R_Enable()
4277 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); in LL_RCC_PLL1R_Disable()
4307 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == RCC_PLL1CFGR_PLL1REN) ? 1UL : 0UL); in LL_RCC_PLL1R_IsEnabled()
Dstm32h5xx_hal_rcc.h264 #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h4183 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); in LL_RCC_PLL1_EnableDomain_SYS()
4198 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); in LL_RCC_PLL1_DisableDomain_SYS()
4209 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == (RCC_PLL1CFGR_PLL1REN)) ? 1UL : 0UL); in LL_RCC_PLL1_IsEnabledDomain_SYS()
Dstm32u5xx_hal_rcc.h332 #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc.c943 …GR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN); in HAL_RCC_OscConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc.c1263 …GR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN); in HAL_RCC_OscConfig()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h6017 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
Dstm32wba52xx.h9791 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
Dstm32wba54xx.h10063 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
Dstm32wba5mxx.h10081 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
Dstm32wba55xx.h10081 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h8518 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
Dstm32h523xx.h12658 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
Dstm32h562xx.h13338 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
Dstm32h533xx.h13177 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
Dstm32h573xx.h15941 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
Dstm32h563xx.h15422 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14508 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk /*!< PLL1 DIVR … macro
Dstm32u535xx.h13995 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk /*!< PLL1 DIVR … macro
Dstm32u575xx.h15403 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk /*!< PLL1 DIVR … macro
Dstm32u585xx.h15965 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk /*!< PLL1 DIVR … macro
Dstm32u595xx.h16431 #define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk /*!< PLL1 DIVR … macro

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