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Searched refs:RCC_PLL1CFGR3_PLL1PDIVEN (Results 1 – 7 of 7) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c2090 SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODSSRST | RCC_PLL1CFGR3_PLL1PDIVEN)); in RCC_PLL_Config()
2141 CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1PDIVEN); in RCC_PLL_Config()
Dstm32n6xx_hal_rcc_ex.c3207 SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODSSRST | RCC_PLL1CFGR3_PLL1PDIVEN)); in HAL_RCCEx_PLLSSCGConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h5259 SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN); in LL_RCC_PLL1P_Enable()
5270 CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN); in LL_RCC_PLL1P_Disable()
5280 …return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN) == RCC_PLL1CFGR3_PLL1PDIVEN) ? 1UL : 0… in LL_RCC_PLL1P_IsEnabled()
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h25400 #define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post… macro
Dstm32n657xx.h26549 #define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post… macro
Dstm32n655xx.h26307 #define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post… macro
Dstm32n647xx.h25642 #define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post… macro