Searched refs:RCC_PLL1CFGR3_PLL1PDIV2 (Results 1 – 10 of 10) sorted by relevance
1674 …pRCC_OscInitStruct->PLL1.PLLP2 = ((cfgr_value & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV… in HAL_RCC_GetOscConfig()2072 MODIFY_REG(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \ in RCC_PLL_Config()2230 else if ((*p_rcc_pll_cfgr3_reg & (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2)) != \ in RCC_PLL_IsNewConfig()
3190 MODIFY_REG(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \ in HAL_RCCEx_PLLSSCGConfig()
316 pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos; in SystemCoreClockUpdate()
373 pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos; in SystemCoreClockUpdate()
25394 #define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO … macro
26543 #define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO … macro
26301 #define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO … macro
25636 #define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO … macro
3641 MODIFY_REG(RCC->PLL1CFGR3, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \3643 ((((__PLLP2__) << RCC_PLL1CFGR3_PLL1PDIV2_Pos) & RCC_PLL1CFGR3_PLL1PDIV2)))); \
5238 MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV2, P2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos); in LL_RCC_PLL1_SetP2()5248 …return (uint32_t)(READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos… in LL_RCC_PLL1_GetP2()