RCC_PLL1CFGR2_DIVP_Pos (reference) in projects: hal_stm32-latest

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Searched refs:RCC_PLL1CFGR2_DIVP_Pos (Results 1 – 25 of 26) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
D	stm32mp1xx_hal_rcc.c	`1782 …Struct->PLL.PLLP = (uint32_t)((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVP) >> RCC_PLL1CFGR2_DIVP_Pos) + 1; in HAL_RCC_GetOscConfig() 2024 …32_t)(pll1vco / ((float)(((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVP) >> RCC_PLL1CFGR2_DIVP_Pos) + 1U))); in HAL_RCC_GetPLL1ClockFreq()`
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
D	stm32mp1xx_ll_rcc.h	`4035 return (uint32_t)((READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_DIVP) >> RCC_PLL1CFGR2_DIVP_Pos) + 1U); in LL_RCC_PLL1_GetP() 4077 MODIFY_REG(RCC->PLL1CFGR2, RCC_PLL1CFGR2_DIVP, (DIVP - 1U) << RCC_PLL1CFGR2_DIVP_Pos); in LL_RCC_PLL1_SetP()`
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
D	stm32mp151dxx_ca7.h	23269 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 23270 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 23272 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 23273 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 23274 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 23275 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 23276 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 23277 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 23278 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp151fxx_cm4.h	23432 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 23433 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 23435 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 23436 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 23437 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 23438 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 23439 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 23440 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 23441 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp151axx_ca7.h	23269 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 23270 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 23272 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 23273 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 23274 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 23275 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 23276 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 23277 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 23278 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp151axx_cm4.h	23235 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 23236 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 23238 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 23239 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 23240 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 23241 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 23242 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 23243 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 23244 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp151dxx_cm4.h	23235 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 23236 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 23238 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 23239 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 23240 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 23241 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 23242 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 23243 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 23244 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp151cxx_ca7.h	23466 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 23467 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 23469 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 23470 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 23471 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 23472 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 23473 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 23474 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 23475 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp151cxx_cm4.h	23432 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 23433 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 23435 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 23436 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 23437 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 23438 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 23439 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 23440 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 23441 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp151fxx_ca7.h	23466 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 23467 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 23469 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 23470 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 23471 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 23472 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 23473 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 23474 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 23475 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp153axx_ca7.h	24820 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 24821 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 24823 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 24824 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 24825 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 24826 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 24827 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 24828 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 24829 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp153axx_cm4.h	24786 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 24787 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 24789 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 24790 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 24791 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 24792 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 24793 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 24794 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 24795 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp153cxx_ca7.h	25017 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 25018 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 25020 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 25021 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 25022 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 25023 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 25024 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 25025 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 25026 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp153cxx_cm4.h	24983 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 24984 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 24986 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 24987 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 24988 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 24989 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 24990 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 24991 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 24992 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp153dxx_ca7.h	24820 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 24821 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 24823 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 24824 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 24825 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 24826 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 24827 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 24828 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 24829 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp153dxx_cm4.h	24786 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 24787 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 24789 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 24790 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 24791 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 24792 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 24793 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 24794 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 24795 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp153fxx_ca7.h	25017 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 25018 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 25020 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 25021 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 25022 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 25023 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 25024 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 25025 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 25026 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp153fxx_cm4.h	24983 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 24984 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 24986 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 24987 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 24988 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 24989 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 24990 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 24991 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 24992 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp157axx_ca7.h	26043 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 26044 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 26046 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 26047 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 26048 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 26049 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 26050 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 26051 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 26052 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp157axx_cm4.h	26009 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 26010 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 26012 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 26013 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 26014 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 26015 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 26016 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 26017 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 26018 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp157cxx_ca7.h	26240 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 26241 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 26243 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 26244 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 26245 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 26246 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 26247 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 26248 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 26249 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp157cxx_cm4.h	26206 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 26207 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 26209 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 26210 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 26211 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 26212 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 26213 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 26214 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 26215 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp157dxx_ca7.h	26043 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 26044 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 26046 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 26047 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 26048 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 26049 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 26050 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 26051 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 26052 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp157dxx_cm4.h	26009 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 26010 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 26012 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 26013 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 26014 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 26015 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 26016 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 26017 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 26018 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …
D	stm32mp157fxx_ca7.h	26240 #define RCC_PLL1CFGR2_DIVP_Pos (0U) macro 26241 #define RCC_PLL1CFGR2_DIVP_Msk (0x7FUL << RCC_PLL1CFGR2_DIVP_Pos) … 26243 #define RCC_PLL1CFGR2_DIVP_0 (0x1UL << RCC_PLL1CFGR2_DIVP_Pos) … 26244 #define RCC_PLL1CFGR2_DIVP_1 (0x2UL << RCC_PLL1CFGR2_DIVP_Pos) … 26245 #define RCC_PLL1CFGR2_DIVP_2 (0x4UL << RCC_PLL1CFGR2_DIVP_Pos) … 26246 #define RCC_PLL1CFGR2_DIVP_3 (0x8UL << RCC_PLL1CFGR2_DIVP_Pos) … 26247 #define RCC_PLL1CFGR2_DIVP_4 (0x10UL << RCC_PLL1CFGR2_DIVP_Pos) … 26248 #define RCC_PLL1CFGR2_DIVP_5 (0x20UL << RCC_PLL1CFGR2_DIVP_Pos) … 26249 #define RCC_PLL1CFGR2_DIVP_6 (0x40UL << RCC_PLL1CFGR2_DIVP_Pos) …

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babblesim_ext_2G4_libPhyComv1-latest
babblesim_ext_2G4_modem_BLE_simple-latest
babblesim_ext_2G4_modem_magic-latest
babblesim_ext_2G4_phy_v1-latest
babblesim_ext_libCryptov1-latest
bsim-latest
cmsis-latest
cmsis-dsp-latest
cmsis-nn-latest
cmsis_6-latest
edtt-latest
fatfs-latest
hal_adi-latest
hal_altera-latest
hal_ambiq-latest
hal_atmel-latest
hal_espressif-latest
hal_ethos_u-latest
hal_gigadevice-latest
hal_infineon-latest
hal_intel-latest
hal_microchip-latest
hal_nordic-latest
hal_nuvoton-latest
hal_nxp-latest
hal_openisa-latest
hal_quicklogic-latest
hal_renesas-latest
hal_rpi_pico-latest
hal_silabs-latest
hal_st-latest
hal_stm32-latest
hal_tdk-latest
hal_telink-latest
hal_ti-latest
hal_wch-latest
hal_wurthelektronik-latest
hal_xtensa-latest
hostap-latest
liblc3-latest
libmctp-latest
libmetal-latest
littlefs-latest
loramac-node-latest
lvgl-latest
mbedtls-latest
mcuboot-latest
mipi-sys-t-latest
net-tools-latest
nrf_hw_models-latest
nrf_wifi-latest
open-amp-latest
openthread-latest
percepio-latest
picolibc-latest
segger-latest
tinycrypt-latest
trusted-firmware-a-latest
trusted-firmware-m-latest
uoscore-uedhoc-latest
zcbor-latest