Searched refs:RCC_PLL1CFGR1_PLL1DIVN_Pos (Results 1 – 10 of 10) sorted by relevance
1669 …C_OscInitStruct->PLL1.PLLN = ((cfgr_value & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos); in HAL_RCC_GetOscConfig()2071 | (pPLLInit->PLLN << RCC_PLL1CFGR1_PLL1DIVN_Pos))); in RCC_PLL_Config()2221 | (pPLLInit->PLLN << RCC_PLL1CFGR1_PLL1DIVN_Pos))) in RCC_PLL_IsNewConfig()
3189 | (pPLLInit->PLLN << RCC_PLL1CFGR1_PLL1DIVN_Pos))); in HAL_RCCEx_PLLSSCGConfig()
312 plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos; in SystemCoreClockUpdate()
369 plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos; in SystemCoreClockUpdate()
25349 #define RCC_PLL1CFGR1_PLL1DIVN_Pos (8U) macro25350 #define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000F…
26498 #define RCC_PLL1CFGR1_PLL1DIVN_Pos (8U) macro26499 #define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000F…
26256 #define RCC_PLL1CFGR1_PLL1DIVN_Pos (8U) macro26257 #define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000F…
25591 #define RCC_PLL1CFGR1_PLL1DIVN_Pos (8U) macro25592 #define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000F…
5174 MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVN, N << RCC_PLL1CFGR1_PLL1DIVN_Pos); in LL_RCC_PLL1_SetN()5185 …return (uint32_t)((READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos)… in LL_RCC_PLL1_GetN()
3639 … | ( (__PLLM__) << RCC_PLL1CFGR1_PLL1DIVM_Pos) | (((__PLLN__) << RCC_PLL1CFGR1_PLL1DIVN_Pos)))); \