Searched refs:RCC_PLL1CFGR1_PLL1DIVN (Results 1 – 10 of 10) sorted by relevance
1669 …pRCC_OscInitStruct->PLL1.PLLN = ((cfgr_value & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_P… in HAL_RCC_GetOscConfig()2069 …(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \ in RCC_PLL_Config()2219 …rcc_pll_cfgr1_reg & (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN)) != \ in RCC_PLL_IsNewConfig()
3187 …(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \ in HAL_RCCEx_PLLSSCGConfig()
312 plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos; in SystemCoreClockUpdate()
369 plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos; in SystemCoreClockUpdate()
25351 #define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 inte… macro
26500 #define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 inte… macro
26258 #define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 inte… macro
25593 #define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 inte… macro
5174 MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVN, N << RCC_PLL1CFGR1_PLL1DIVN_Pos); in LL_RCC_PLL1_SetN()5185 …return (uint32_t)((READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos)… in LL_RCC_PLL1_GetN()
3638 …RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1BYP | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \