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Searched refs:RCC_PLL1CFGR1_PLL1DIVM_Pos (Results 1 – 10 of 10) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c1668 …C_OscInitStruct->PLL1.PLLM = ((cfgr_value & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos); in HAL_RCC_GetOscConfig()
2070 (pPLLInit->PLLSource | (pPLLInit->PLLM << RCC_PLL1CFGR1_PLL1DIVM_Pos) \ in RCC_PLL_Config()
2220 (pPLLInit->PLLSource | (pPLLInit->PLLM << RCC_PLL1CFGR1_PLL1DIVM_Pos) \ in RCC_PLL_IsNewConfig()
Dstm32n6xx_hal_rcc_ex.c3188 (pPLLInit->PLLSource | (pPLLInit->PLLM << RCC_PLL1CFGR1_PLL1DIVM_Pos) \ in HAL_RCCEx_PLLSSCGConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c311 pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos; in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c368 pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos; in SystemCoreClockUpdate()
Dstm32n645xx.h25352 #define RCC_PLL1CFGR1_PLL1DIVM_Pos (20U) macro
25353 #define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F000…
Dstm32n657xx.h26501 #define RCC_PLL1CFGR1_PLL1DIVM_Pos (20U) macro
26502 #define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F000…
Dstm32n655xx.h26259 #define RCC_PLL1CFGR1_PLL1DIVM_Pos (20U) macro
26260 #define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F000…
Dstm32n647xx.h25594 #define RCC_PLL1CFGR1_PLL1DIVM_Pos (20U) macro
25595 #define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F000…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h5196 MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVM, M << RCC_PLL1CFGR1_PLL1DIVM_Pos); in LL_RCC_PLL1_SetM()
5206 return (uint32_t)(READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos); in LL_RCC_PLL1_GetM()
Dstm32n6xx_hal_rcc.h3639 …((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL1CFGR1_PLL1DIVM_Pos) | (((__PLLN__) << RCC_PLL1CFGR1_PLL…